itrace_dsp_events_pmu.h

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#ifndef ITRACE_DSP_EVENTS_PMU_H
#define ITRACE_DSP_EVENTS_PMU_H

#include "itrace_types.h"

#define DUMMY_DSP_PMU_EVENT_FIRST 0x7fff

#define ITRACE_DSP_EVENT_PMU_COUNTER0_OVERFLOW 0x8000

#define ITRACE_DSP_EVENT_PMU_COUNTER2_OVERFLOW 0x8001

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_ANY 0x8002

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_BSB 0x8003

#define ITRACE_DSP_EVENT_PMU_COUNTER4_OVERFLOW 0x8004

#define ITRACE_DSP_EVENT_PMU_COUNTER6_OVERFLOW 0x8005

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_B2B 0x8006

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_SMT 0x8007

#define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS 0x8008

#define ITRACE_DSP_EVENT_PMU_DCACHE_DEMAND_MISS 0x8009

#define ITRACE_DSP_EVENT_PMU_DCACHE_STORE_MISS 0x800a

#define ITRACE_DSP_EVENT_PMU_CU_PKT_READY_NOT_DISPATCHED 0x800b

#define ITRACE_DSP_EVENT_PMU_ANY_IU_REPLAY 0x800c

#define ITRACE_DSP_EVENT_PMU_ANY_DU_REPLAY 0x800d

#define ITRACE_DSP_EVENT_PMU_ISSUED_PACKETS 0x800e

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_1_THREAD_RUNNING 0x800f

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_2_THREAD_RUNNING 0x8010

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_3_THREAD_RUNNING 0x8011

#define ITRACE_DSP_EVENT_PMU_COMMITTED_INSTS 0x8012

#define ITRACE_DSP_EVENT_PMU_COMMITTED_TC1_INSTS 0x8013

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PRIVATE_INSTS 0x8014

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING 0x8015

#define ITRACE_DSP_EVENT_PMU_COMMITTED_LOADS 0x8016

#define ITRACE_DSP_EVENT_PMU_COMMITTED_STORES 0x8017

#define ITRACE_DSP_EVENT_PMU_COMMITTED_MEMOPS 0x8018

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PROGRAM_FLOW_INSTS 0x8019

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_CHANGED_FLOW 0x801a

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_ENDLOOP 0x801b

#define ITRACE_DSP_EVENT_PMU_CYCLES_1_THREAD_RUNNING 0x801c

#define ITRACE_DSP_EVENT_PMU_CYCLES_2_THREAD_RUNNING 0x801d

#define ITRACE_DSP_EVENT_PMU_CYCLES_3_THREAD_RUNNING 0x801e

#define ITRACE_DSP_EVENT_PMU_CYCLES_4_THREAD_RUNNING 0x801f

#define ITRACE_DSP_EVENT_PMU_AXI_READ_REQUEST 0x8020

#define ITRACE_DSP_EVENT_PMU_AXI_LINE32_READ_REQUEST 0x8021

#define ITRACE_DSP_EVENT_PMU_AXI_WRITE_REQUEST 0x8022

#define ITRACE_DSP_EVENT_PMU_AXI_LINE32_WRITE_REQUEST 0x8023

#define ITRACE_DSP_EVENT_PMU_AHB_READ_REQUEST 0x8024

#define ITRACE_DSP_EVENT_PMU_AHB_WRITE_REQUEST 0x8025

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS 0x8026

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS 0x8027

#define ITRACE_DSP_EVENT_PMU_AXI2_READ_REQUEST 0x8028

#define ITRACE_DSP_EVENT_PMU_AXI2_LINE32_READ_REQUEST 0x8029

#define ITRACE_DSP_EVENT_PMU_AXI2_WRITE_REQUEST 0x802a

#define ITRACE_DSP_EVENT_PMU_AXI2_LINE32_WRITE_REQUEST 0x802b

#define ITRACE_DSP_EVENT_PMU_AXI2_CONGESTION 0x802c

#define ITRACE_DSP_EVENT_PMU_COMMITTED_FPS 0x802d

#define ITRACE_DSP_EVENT_PMU_REDIRECT_BIMODAL_MISPREDICT 0x802e

#define ITRACE_DSP_EVENT_PMU_REDIRECT_TARGET_MISPREDICT 0x802f

#define ITRACE_DSP_EVENT_PMU_REDIRECT_LOOP_MISPREDICT 0x8030

#define ITRACE_DSP_EVENT_PMU_REDIRECT_MISC 0x8031

#define ITRACE_DSP_EVENT_PMU_JTLB_MISS 0x8032

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_RETURN 0x8033

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_INDIRECT_JUMP 0x8034

#define ITRACE_DSP_EVENT_PMU_COMMITTED_BIMODAL_BRANCH_INSTS 0x8035

#define ITRACE_DSP_EVENT_PMU_ICACHE_ACCESS 0x8036

#define ITRACE_DSP_EVENT_PMU_BTB_HIT 0x8037

#define ITRACE_DSP_EVENT_PMU_BTB_MISS 0x8038

#define ITRACE_DSP_EVENT_PMU_IU_DEMAND_SECONDARY_MISS 0x8039

#define ITRACE_DSP_EVENT_PMU_FAST_FETCH_KILLED 0x803a

#define ITRACE_DSP_EVENT_PMU_FETCHED_PACKETS_DROPPED 0x803b

#define ITRACE_DSP_EVENT_PMU_IU_PREFETCHES_SENT_TO_L2 0x803c

#define ITRACE_DSP_EVENT_PMU_ITLB_MISS 0x803d

#define ITRACE_DSP_EVENT_PMU_FETCH_2_CYCLE 0x803e

#define ITRACE_DSP_EVENT_PMU_FETCH_3_CYCLE 0x803f

#define ITRACE_DSP_EVENT_PMU_L2_IU_SECONDARY_MISS 0x8040

#define ITRACE_DSP_EVENT_PMU_L2_IU_ACCESS 0x8041

#define ITRACE_DSP_EVENT_PMU_L2_IU_MISS 0x8042

#define ITRACE_DSP_EVENT_PMU_L2_IU_PREFETCH_ACCESS 0x8043

#define ITRACE_DSP_EVENT_PMU_L2_IU_PREFETCH_MISS 0x8044

#define ITRACE_DSP_EVENT_PMU_L2_DU_READ_ACCESS 0x8045

#define ITRACE_DSP_EVENT_PMU_L2_DU_READ_MISS 0x8046

#define ITRACE_DSP_EVENT_PMU_L2FETCH_ACCESS 0x8047

#define ITRACE_DSP_EVENT_PMU_L2FETCH_MISS 0x8048

#define ITRACE_DSP_EVENT_PMU_L2_ACCESS 0x8049

#define ITRACE_DSP_EVENT_PMU_L2_TAG_ARRAY_CONFLICT 0x804a

#define ITRACE_DSP_EVENT_PMU_TCM_DU_ACCESS 0x804b

#define ITRACE_DSP_EVENT_PMU_TCM_DU_READ_ACCESS 0x804c

#define ITRACE_DSP_EVENT_PMU_TCM_IU_ACCESS 0x804d

#define ITRACE_DSP_EVENT_PMU_L2_CASTOUT 0x804e

#define ITRACE_DSP_EVENT_PMU_L2_DU_STORE_ACCESS 0x804f

#define ITRACE_DSP_EVENT_PMU_L2_DU_STORE_MISS 0x8050

#define ITRACE_DSP_EVENT_PMU_L2_DU_PREFETCH_ACCESS 0x8051

#define ITRACE_DSP_EVENT_PMU_L2_DU_PREFETCH_MISS 0x8052

#define ITRACE_DSP_EVENT_PMU_L2_DU_LOAD_SECONDARY_MISS 0x8053

#define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND 0x8054

#define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND_KILLED 0x8055

#define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND_OVERWRITE 0x8056

#define ITRACE_DSP_EVENT_PMU_L2FETCH_ACCESS_CREDIT_FAIL 0x8057

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_READ_BUSY 0x8058

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_WRITE_BUSY 0x8059

#define ITRACE_DSP_EVENT_PMU_L2_ACCESS_EVEN 0x805a

#define ITRACE_DSP_EVENT_PMU_CLADE_HIGH_PRIO_L2_ACCESS 0x805b

#define ITRACE_DSP_EVENT_PMU_CLADE_LOW_PRIO_L2_ACCESS 0x805c

#define ITRACE_DSP_EVENT_PMU_CLADE_HIGH_PRIO_L2_MISS 0x805d

#define ITRACE_DSP_EVENT_PMU_CLADE_LOW_PRIO_L2_MISS 0x805e

#define ITRACE_DSP_EVENT_PMU_CLADE_HIGH_PRIO_EXCEPTION 0x805f

#define ITRACE_DSP_EVENT_PMU_CLADE_LOW_PRIO_EXCEPTION 0x8060

#define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_READ_BUSY 0x8061

#define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_WRITE_BUSY 0x8062

#define ITRACE_DSP_EVENT_PMU_ANY_DU_STALL 0x8063

#define ITRACE_DSP_EVENT_PMU_DU_BANK_CONFLICT_REPLAY 0x8064

#define ITRACE_DSP_EVENT_PMU_DU_CREDIT_REPLAY 0x8065

#define ITRACE_DSP_EVENT_PMU_L2_FIFO_FULL_REPLAY 0x8066

#define ITRACE_DSP_EVENT_PMU_DU_STORE_BUFFER_FULL_REPLAY 0x8067

#define ITRACE_DSP_EVENT_PMU_DU_SNOOP_REQUEST 0x8068

#define ITRACE_DSP_EVENT_PMU_DU_FILL_REPLAY 0x8069

#define ITRACE_DSP_EVENT_PMU_DU_READ_TO_L2 0x806a

#define ITRACE_DSP_EVENT_PMU_DU_WRITE_TO_L2 0x806b

#define ITRACE_DSP_EVENT_PMU_DCZERO_COMMITTED 0x806c

#define ITRACE_DSP_EVENT_PMU_DTLB_MISS 0x806d

#define ITRACE_DSP_EVENT_PMU_STORE_BUFFER_HIT_REPLAY 0x806e

#define ITRACE_DSP_EVENT_PMU_STORE_BUFFER_FORCE_REPLAY 0x806f

#define ITRACE_DSP_EVENT_PMU_SMT_BANK_CONFLICT 0x8070

#define ITRACE_DSP_EVENT_PMU_PORT_CONFLICT_REPLAY 0x8071

#define ITRACE_DSP_EVENT_PMU_PAGE_CROSS_REPLAY 0x8072

#define ITRACE_DSP_EVENT_PMU_DU_DEMAND_SECONDARY_MISS 0x8073

#define ITRACE_DSP_EVENT_PMU_DU_MISC_REPLAY 0x8074

#define ITRACE_DSP_EVENT_PMU_DCFETCH_COMMITTED 0x8075

#define ITRACE_DSP_EVENT_PMU_DCFETCH_HIT 0x8076

#define ITRACE_DSP_EVENT_PMU_DCFETCH_MISS 0x8077

#define ITRACE_DSP_EVENT_PMU_DU_LOAD_UNCACHEABLE 0x8078

#define ITRACE_DSP_EVENT_PMU_DU_DUAL_LOAD_UNCACHEABLE 0x8079

#define ITRACE_DSP_EVENT_PMU_DU_STORE_UNCACHEABLE 0x807a

#define ITRACE_DSP_EVENT_PMU_AXI_LINE64_READ_REQUEST 0x807b

#define ITRACE_DSP_EVENT_PMU_AXI_LINE64_WRITE_REQUEST 0x807c

#define ITRACE_DSP_EVENT_PMU_AHB_8_READ_REQUEST 0x807d

#define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND_PAGE_TERMINATION 0x807e

#define ITRACE_DSP_EVENT_PMU_L2_DU_STORE_COALESCE 0x807f

#define ITRACE_DSP_EVENT_PMU_L2_STORE_LINK 0x8080

#define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_70_PERCENT_FULL 0x8081

#define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_80_PERCENT_FULL 0x8082

#define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_90_PERCENT_FULL 0x8083

#define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_FULL_REJECT 0x8084

#define ITRACE_DSP_EVENT_PMU_L2_EVICTION_BUFFERS_FULL 0x8085

#define ITRACE_DSP_EVENT_PMU_AHB_MULTI_BEAT_READ_REQUEST 0x8086

#define ITRACE_DSP_EVENT_PMU_L2_DU_LOAD_SECONDARY_MISS_ON_SW_PREFETCH 0x8087

#define ITRACE_DSP_EVENT_PMU_ARCH_LOCK_PVIEW_CYCLES 0x8088

#define ITRACE_DSP_EVENT_PMU_REDIRECT_PVIEW_CYCLES 0x8089

#define ITRACE_DSP_EVENT_PMU_IU_NO_PKT_PVIEW_CYCLES 0x808a

#define ITRACE_DSP_EVENT_PMU_DU_CACHE_MISS_PVIEW_CYCLES 0x808b

#define ITRACE_DSP_EVENT_PMU_DU_BUSY_OTHER_PVIEW_CYCLES 0x808c

#define ITRACE_DSP_EVENT_PMU_CU_BUSY_PVIEW_CYCLES 0x808d

#define ITRACE_DSP_EVENT_PMU_DU_UNCACHED_PVIEW_CYCLES 0x808e

#define ITRACE_DSP_EVENT_PMU_HVX_ACTIVE 0x808f

#define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_XE 0x8090

#define ITRACE_DSP_EVENT_PMU_CU_REDISPATCH 0x8091

#define ITRACE_DSP_EVENT_PMU_VTCM_SCALAR_FIFO_FULL_CYCLES 0x8092

#define ITRACE_DSP_EVENT_PMU_COPROC_ACTIVE 0x8093

#define ITRACE_DSP_EVENT_PMU_COPROC_ENABLED 0x8094

#define ITRACE_DSP_EVENT_PMU_L2_PIPE_CONFLICT 0x8095

#define ITRACE_DSP_EVENT_PMU_DU_SECMISS_REPLAY 0x8096

#define ITRACE_DSP_EVENT_PMU_DU_DEALLOC_SECURITY_REPLAY 0x8097

#define ITRACE_DSP_EVENT_PMU_THREAD_OFF_PVIEW_CYCLES 0x8098

#define ITRACE_DSP_EVENT_PMU_SMT_DU_CONFLICT_PVIEW_CYCLES 0x8099

#define ITRACE_DSP_EVENT_PMU_SMT_XU_CONFLICT_PVIEW_CYCLES 0x809a

#define ITRACE_DSP_EVENT_PMU_HVX_WAIT_EMPTY 0x809b

#define ITRACE_DSP_EVENT_PMU_HVX_EMPTY 0x809c

#define ITRACE_DSP_EVENT_PMU_HVX_WAIT 0x809d

#define ITRACE_DSP_EVENT_PMU_HVX_REG_ORDER 0x809e

#define ITRACE_DSP_EVENT_PMU_HVX_LD_VTCM_OUTSTANDING 0x809f

#define ITRACE_DSP_EVENT_PMU_HVX_LD_L2_OUTSTANDING 0x80a0

#define ITRACE_DSP_EVENT_PMU_HVX_ST_VTCM_OUTSTANDING 0x80a1

#define ITRACE_DSP_EVENT_PMU_HVX_ST_L2_OUTSTANDING 0x80a2

#define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_OUTSTANDING 0x80a3

#define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_SHARED_FULL 0x80a4

#define ITRACE_DSP_EVENT_PMU_HVX_ST_L2_SHARED_FULL 0x80a5

#define ITRACE_DSP_EVENT_PMU_HVX_ST_ST_BANK_CONFLICT 0x80a6

#define ITRACE_DSP_EVENT_PMU_HVX_VTCM_BANDWIDTH_OVER 0x80a7

#define ITRACE_DSP_EVENT_PMU_HVX_OTHER_PART_OUTSTANDING 0x80a8

#define ITRACE_DSP_EVENT_PMU_HVX_VOLTAGE_UNDER 0x80a9

#define ITRACE_DSP_EVENT_PMU_HVX_POWER_OVER 0x80aa

#define ITRACE_DSP_EVENT_PMU_HVX_PARTIAL_PKT 0x80ab

#define ITRACE_DSP_EVENT_PMU_HVX_PKT 0x80ac

#define ITRACE_DSP_EVENT_PMU_HVX_PKT_THREAD 0x80ad

#define ITRACE_DSP_EVENT_PMU_HVX_CORE_VFIFO_FULL_STALL 0x80ae

#define ITRACE_DSP_EVENT_PMU_HVX_L2_STORE_ACCESS 0x80af

#define ITRACE_DSP_EVENT_PMU_HVX_L2_STORE_MISS 0x80b0

#define ITRACE_DSP_EVENT_PMU_HVX_L2_LOAD_ACCESS 0x80b1

#define ITRACE_DSP_EVENT_PMU_HVX_L2_LOAD_MISS 0x80b2

#define ITRACE_DSP_EVENT_PMU_HVX_L2_LOAD_SECONDARY_MISS 0x80b3

#define ITRACE_DSP_EVENT_PMU_HVX_TCM_STORE_ACCESS 0x80b4

#define ITRACE_DSP_EVENT_PMU_HVX_TCM_LOAD_ACCESS 0x80b5

#define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_EXEC 0x80b6

#define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_1_VMEM 0x80b7

#define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_2_VMEM 0x80b8

#define ITRACE_DSP_EVENT_PMU_COPROC0_REPLAY 0x80b9

#define ITRACE_DSP_EVENT_PMU_COPROC0_IDLE 0x80ba

#define ITRACE_DSP_EVENT_PMU_COPROC0_FIFO_FULL_REPLAY 0x80bb

#define ITRACE_DSP_EVENT_PMU_COPROC0_AXISLAVE_ACCESS 0x80bc

#define ITRACE_DSP_EVENT_PMU_COPROC0_VEXTRACT_STALL 0x80bd

#define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_1_VEXTRACT 0x80be

#define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_2_VEXTRACT 0x80bf

#define ITRACE_DSP_EVENT_PMU_COPROC0_FIFO_DISPATCH 0x80c0

#define ITRACE_DSP_EVENT_PMU_COPROC0_CYCLES_RUNNING 0x80c1

#define ITRACE_DSP_EVENT_PMU_COPROC0_REG_INTERLOCK_REPLAY 0x80c2

#define ITRACE_DSP_EVENT_PMU_COPROC0_MNOC_AXI_REPLAY 0x80c3

#define ITRACE_DSP_EVENT_PMU_COPROC0_RFIFO_REPLAY 0x80c4

#define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_XE 0x80c5

#define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_EXEC 0x80c6

#define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_1_VMEM 0x80c7

#define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_2_VMEM 0x80c8

#define ITRACE_DSP_EVENT_PMU_COPROC1_REPLAY 0x80c9

#define ITRACE_DSP_EVENT_PMU_COPROC1_IDLE 0x80ca

#define ITRACE_DSP_EVENT_PMU_COPROC1_FIFO_FULL_REPLAY 0x80cb

#define ITRACE_DSP_EVENT_PMU_COPROC1_VEXTRACT_STALL 0x80cc

#define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_1_VEXTRACT 0x80cd

#define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_2_VEXTRACT 0x80ce

#define ITRACE_DSP_EVENT_PMU_COPROC1_FIFO_DISPATCH 0x80cf

#define ITRACE_DSP_EVENT_PMU_COPROC1_CYCLES_RUNNING 0x80d0

#define ITRACE_DSP_EVENT_PMU_COPROC1_REG_INTERLOCK_REPLAY 0x80d1

#define ITRACE_DSP_EVENT_PMU_IU_L1S_ACCESS 0x80d2

#define ITRACE_DSP_EVENT_PMU_IU_L1S_PREFETCH 0x80d3

#define ITRACE_DSP_EVENT_PMU_IU_L1S_AXIS_STALL 0x80d4

#define ITRACE_DSP_EVENT_PMU_IU_L1S_NO_GRANT 0x80d5

#define ITRACE_DSP_EVENT_PMU_LOOPCACHE_PACKETS 0x80d6

#define ITRACE_DSP_EVENT_PMU_AXI_LINE128_READ_REQUEST 0x80d7

#define ITRACE_DSP_EVENT_PMU_AXI_LINE128_WRITE_REQUEST 0x80d8

#define ITRACE_DSP_EVENT_PMU_NUM_PACKET_CRACKED 0x80d9

#define ITRACE_DSP_EVENT_PMU_DU_STORE_LINK 0x80da

#define ITRACE_DSP_EVENT_PMU_DU_L1S_LOAD_ACCESS 0x80db

#define ITRACE_DSP_EVENT_PMU_TAG_WRITE_CONFLICT_REPLAY 0x80dc

#define ITRACE_DSP_EVENT_PMU_L2FETCH_DROP 0x80dd

#define ITRACE_DSP_EVENT_PMU_COPROC_BUSY_PVIEW_CYCLES 0x80de

#define ITRACE_DSP_EVENT_PMU_SYSTEM_BUSY_PVIEW_CYCLES 0x80df

#define ITRACE_DSP_EVENT_PMU_HVX_ST_DWR_BANK_CONFLICT 0x80e0

#define ITRACE_DSP_EVENT_PMU_COPROC0_FIFO_FULL_STALL 0x80e1

#define ITRACE_DSP_EVENT_PMU_COPROC0_IU_REPLAY 0x80e2

#define ITRACE_DSP_EVENT_PMU_COPROC0_IU_L1S_REQUEST 0x80e3

#define ITRACE_DSP_EVENT_PMU_COPROC1_FIFO_FULL_STALL 0x80e4

#define ITRACE_DSP_EVENT_PMU_COPROC1_MNOC_AXI_REPLAY 0x80e5

#define ITRACE_DSP_EVENT_PMU_COPROC1_RFIFO_REPLAY 0x80e6

#define ITRACE_DSP_EVENT_PMU_CYCLES_5_THREAD_RUNNING 0x80e7

#define ITRACE_DSP_EVENT_PMU_CYCLES_6_THREAD_RUNNING 0x80e8

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T0 0x80e9

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T1 0x80ea

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T2 0x80eb

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T3 0x80ec

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T4 0x80ed

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T5 0x80ee

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_5_THREAD_RUNNING 0x80ef

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_6_THREAD_RUNNING 0x80f0

#define ITRACE_DSP_EVENT_PMU_THREAD_LMH_THROTTLE 0x80f1

#define ITRACE_DSP_EVENT_PMU_LMH_THROTTLE 0x80f2

#define ITRACE_DSP_EVENT_PMU_GLOBAL_POWERLIMITS_OVER 0x80f3

#define ITRACE_DSP_EVENT_PMU_COMMITTED_NOPS 0x80f4

#define ITRACE_DSP_EVENT_PMU_ISSUED_INSTS 0x80f5

#define ITRACE_DSP_EVENT_PMU_DISPATCHED_PACKETS 0x80f6

#define ITRACE_DSP_EVENT_PMU_DISPATCHED_INSTS 0x80f7

#define ITRACE_DSP_EVENT_PMU_AXI_LINE256_WRITE_REQUEST 0x80f8

#define ITRACE_DSP_EVENT_PMU_VTCM_FIFO_FULL_CYCLES 0x80f9

#define ITRACE_DSP_EVENT_PMU_L2ITCM_IU_READ 0x80fa

#define ITRACE_DSP_EVENT_PMU_L2ITCM_DU_READ 0x80fb

#define ITRACE_DSP_EVENT_PMU_L2ITCM_DU_WRITE 0x80fc

#define ITRACE_DSP_EVENT_PMU_L2ITCM_BIMODAL_WRITES_SUCCESS 0x80fd

#define ITRACE_DSP_EVENT_PMU_L2ITCM_BIMODAL_WRITES_DROPPED 0x80fe

#define ITRACE_DSP_EVENT_PMU_L2ITCM_IU_PREFETCH_READ 0x80ff

#define ITRACE_DSP_EVENT_PMU_GUARDBUF_SETMATCH_CRACKING_REPLAY 0x8100

#define ITRACE_DSP_EVENT_PMU_DCACHE_EVICTION_IN_PIPE_REPLAY 0x8101

#define ITRACE_DSP_EVENT_PMU_STBUF_MATCH_PARTIAL_CRACK_REPLAY 0x8102

#define ITRACE_DSP_EVENT_PMU_DU_STORE_RELEASE_CREDIT_STALL 0x8103

#define ITRACE_DSP_EVENT_PMU_AXI_LINE256_READ_REQUEST 0x8104

#define ITRACE_DSP_EVENT_PMU_AXI_LINE128_READ_REQUEST_EVEN 0x8105

#define ITRACE_DSP_EVENT_PMU_AXI_READ_REQUEST_EVEN 0x8106

#define ITRACE_DSP_EVENT_PMU_AXI_LINE32_READ_REQUEST_EVEN 0x8107

#define ITRACE_DSP_EVENT_PMU_AXI_WRITE_REQUEST_EVEN 0x8108

#define ITRACE_DSP_EVENT_PMU_AXI_LINE32_WRITE_REQUEST_EVEN 0x8109

#define ITRACE_DSP_EVENT_PMU_AXI_LINE128_WRITE_REQUEST_EVEN 0x810a

#define ITRACE_DSP_EVENT_PMU_AXI_LINE64_READ_REQUEST_EVEN 0x810b

#define ITRACE_DSP_EVENT_PMU_AXI_LINE64_WRITE_REQUEST_EVEN 0x810c

#define ITRACE_DSP_EVENT_PMU_AXI_WR_CONGESTION_EVEN 0x810d

#define ITRACE_DSP_EVENT_PMU_AXI_INCOMPLETE_WRITE_REQUEST_EVEN 0x810e

#define ITRACE_DSP_EVENT_PMU_AXI_LINE256_READ_REQUEST_EVEN 0x810f

#define ITRACE_DSP_EVENT_PMU_AXI_LINE256_WRITE_REQUEST_EVEN 0x8110

#define ITRACE_DSP_EVENT_PMU_CYCLES_3_COPROC_THREADS_ONE_CLUSTER 0x8111

#define ITRACE_DSP_EVENT_PMU_HVX_ACC_ORDER 0x8112

#define ITRACE_DSP_EVENT_PMU_HVX_VTCM_OUTSTANDING 0x8113

#define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_FULL 0x8114

#define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_IN_FULL 0x8115

#define ITRACE_DSP_EVENT_PMU_HVX_ST_FULL 0x8116

#define ITRACE_DSP_EVENT_PMU_HVX_VOLTAGE_VIRUS_OVER 0x8117

#define ITRACE_DSP_EVENT_PMU_HVX_PKT_PARTIAL 0x8118

#define ITRACE_DSP_EVENT_PMU_HVXLD_L2 0x8119

#define ITRACE_DSP_EVENT_PMU_HVXLD_L2_TCM 0x811a

#define ITRACE_DSP_EVENT_PMU_HVXLD_L2_MISS 0x811b

#define ITRACE_DSP_EVENT_PMU_HVXLD_L2_SECONDARY_MISS 0x811c

#define ITRACE_DSP_EVENT_PMU_HVXST_L2_WR 0x811d

#define ITRACE_DSP_EVENT_PMU_HVXST_SLD_CONFLICT 0x811e

#define ITRACE_DSP_EVENT_PMU_HVXST_VTCM_GATH_CONFLICT 0x811f

#define ITRACE_DSP_EVENT_PMU_HVXST_L2_CONFLICT 0x8120

#define ITRACE_DSP_EVENT_PMU_HVXST_VTCM_CONFLICT 0x8121

#define ITRACE_DSP_EVENT_PMU_HVXST_L2_FULL 0x8122

#define ITRACE_DSP_EVENT_PMU_HVXST_VTCM_FULL 0x8123

#define ITRACE_DSP_EVENT_PMU_HVXST_L2 0x8124

#define ITRACE_DSP_EVENT_PMU_HVXST_L2_MISS 0x8125

#define ITRACE_DSP_EVENT_PMU_HVXST_L2TCM 0x8126

#define ITRACE_DSP_EVENT_PMU_HVXST_VTCM 0x8127

#define ITRACE_DSP_EVENT_PMU_HVXST_L2_SECODARY_MISS 0x8128

#define ITRACE_DSP_EVENT_PMU_HVXPIPE_ALU 0x8129

#define ITRACE_DSP_EVENT_PMU_HVXPIPE_MPY 0x812a

#define ITRACE_DSP_EVENT_PMU_HVXPIPE_SHIFT 0x812b

#define ITRACE_DSP_EVENT_PMU_HVXPIPE_PERM 0x812c

#define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_XE 0x812d

#define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_EXEC 0x812e

#define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_1_VMEM 0x812f

#define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_2_VMEM 0x8130

#define ITRACE_DSP_EVENT_PMU_COPROC2_REPLAY 0x8131

#define ITRACE_DSP_EVENT_PMU_COPROC2_IDLE 0x8132

#define ITRACE_DSP_EVENT_PMU_COPROC2_FIFO_FULL_STALL 0x8133

#define ITRACE_DSP_EVENT_PMU_COPROC2_VEXTRACT_STALL 0x8134

#define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_1_VEXTRACT 0x8135

#define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_2_VEXTRACT 0x8136

#define ITRACE_DSP_EVENT_PMU_COPROC2_FIFO_DISPATCH 0x8137

#define ITRACE_DSP_EVENT_PMU_COPROC2_CYCLES_RUNNING 0x8138

#define ITRACE_DSP_EVENT_PMU_COPROC2_REG_INTERLOCK_REPLAY 0x8139

#define ITRACE_DSP_EVENT_PMU_COPROC2_MNOC_AXI_REPLAY 0x813a

#define ITRACE_DSP_EVENT_PMU_COPROC2_RFIFO_REPLAY 0x813b

#define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_XE 0x813c

#define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_EXEC 0x813d

#define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_1_VMEM 0x813e

#define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_2_VMEM 0x813f

#define ITRACE_DSP_EVENT_PMU_COPROC3_REPLAY 0x8140

#define ITRACE_DSP_EVENT_PMU_COPROC3_IDLE 0x8141

#define ITRACE_DSP_EVENT_PMU_COPROC3_FIFO_FULL_STALL 0x8142

#define ITRACE_DSP_EVENT_PMU_COPROC3_VEXTRACT_STALL 0x8143

#define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_1_VEXTRACT 0x8144

#define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_2_VEXTRACT 0x8145

#define ITRACE_DSP_EVENT_PMU_COPROC3_FIFO_DISPATCH 0x8146

#define ITRACE_DSP_EVENT_PMU_COPROC3_CYCLES_RUNNING 0x8147

#define ITRACE_DSP_EVENT_PMU_COPROC3_REG_INTERLOCK_REPLAY 0x8148

#define ITRACE_DSP_EVENT_PMU_COPROC3_MNOC_AXI_REPLAY 0x8149

#define ITRACE_DSP_EVENT_PMU_COPROC3_RFIFO_REPLAY 0x814a

#define ITRACE_DSP_EVENT_PMU_HMX_ACTIVE 0x814b

#define ITRACE_DSP_EVENT_PMU_HMX_CVT_FULL 0x814c

#define ITRACE_DSP_EVENT_PMU_HMX_MAC_FULL 0x814d

#define ITRACE_DSP_EVENT_PMU_HMX_DROP 0x814e

#define ITRACE_DSP_EVENT_PMU_HMX_CVT 0x814f

#define ITRACE_DSP_EVENT_PMU_HMX_MAC 0x8150

#define ITRACE_DSP_EVENT_PMU_HMX_MXFIFO_FULL 0x8151

#define ITRACE_DSP_EVENT_PMU_HMXMAC_FULL 0x8152

#define ITRACE_DSP_EVENT_PMU_HMXMAC_ACT_OUTSTANDING 0x8153

#define ITRACE_DSP_EVENT_PMU_HMXMAC_WGT_OUTSTANDING 0x8154

#define ITRACE_DSP_EVENT_PMU_HMXMAC_MULT_DROP 0x8155

#define ITRACE_DSP_EVENT_PMU_HMXMAC_POWER_OVER 0x8156

#define ITRACE_DSP_EVENT_PMU_HMXMAC_FXP_PARTIAL 0x8157

#define ITRACE_DSP_EVENT_PMU_HMXMAC_FLT_PARTIAL 0x8158

#define ITRACE_DSP_EVENT_PMU_HMXMAC_DRAIN_PARTIAL 0x8159

#define ITRACE_DSP_EVENT_PMU_HMXMAC_FXP 0x815a

#define ITRACE_DSP_EVENT_PMU_HMXMAC_FLT 0x815b

#define ITRACE_DSP_EVENT_PMU_HMXMAC_DRAIN 0x815c

#define ITRACE_DSP_EVENT_PMU_HMXCVT_ORDER 0x815d

#define ITRACE_DSP_EVENT_PMU_HMXCVT_BUSY 0x815e

#define ITRACE_DSP_EVENT_PMU_HMXCVT_LD_OUTSTANDING 0x815f

#define ITRACE_DSP_EVENT_PMU_HMXCVT_WR_FULL 0x8160

#define ITRACE_DSP_EVENT_PMU_HMXCVT_VOLTAGE_UNDER 0x8161

#define ITRACE_DSP_EVENT_PMU_HMXCVT_POWER_OVER 0x8162

#define ITRACE_DSP_EVENT_PMU_HMXCVT_FXP_PARTIAL 0x8163

#define ITRACE_DSP_EVENT_PMU_HMXCVT_FLT_PARTIAL 0x8164

#define ITRACE_DSP_EVENT_PMU_HMXCVT_LD 0x8165

#define ITRACE_DSP_EVENT_PMU_HMXCVT_FXP 0x8166

#define ITRACE_DSP_EVENT_PMU_HMXCVT_FLT 0x8167

#define ITRACE_DSP_EVENT_PMU_HMXCVT_ST 0x8168

#define ITRACE_DSP_EVENT_PMU_HMXCVT_CLR 0x8169

#define ITRACE_DSP_EVENT_PMU_HMXARRAY_FXP_MPY 0x816a

#define ITRACE_DSP_EVENT_PMU_HMXARRAY_FLT_MPY 0x816b

#define ITRACE_DSP_EVENT_PMU_HMXARRAY_FXP_ACC 0x816c

#define ITRACE_DSP_EVENT_PMU_HMXARRAY_FLT_ACC 0x816d

#define ITRACE_DSP_EVENT_PMU_HMXARRAY_FXP_CVT 0x816e

#define ITRACE_DSP_EVENT_PMU_HMXARRAY_FLT_CVT 0x816f

#define ITRACE_DSP_EVENT_PMU_UDMA_ACTIVE_CYCLES 0x8170

#define ITRACE_DSP_EVENT_PMU_UDMA_STALL_DESCRIPTOR_FETCH 0x8171

#define ITRACE_DSP_EVENT_PMU_UDMA_STALL_TLB_MISS 0x8172

#define ITRACE_DSP_EVENT_PMU_UDMA_STALL_MONITOR_GUEST_MODE 0x8173

#define ITRACE_DSP_EVENT_PMU_UDMA_DMPOLL_CYCLES 0x8174

#define ITRACE_DSP_EVENT_PMU_UDMA_DMWAIT_CYCLES 0x8175

#define ITRACE_DSP_EVENT_PMU_UDMA_SYNCHT_CYCLES 0x8176

#define ITRACE_DSP_EVENT_PMU_UDMA_TLBSYNCH_CYCLES 0x8177

#define ITRACE_DSP_EVENT_PMU_UDMA_TLB_MISS 0x8178

#define ITRACE_DSP_EVENT_PMU_UDMA_DESCRIPTOR_DONE 0x8179

#define ITRACE_DSP_EVENT_PMU_UDMA_DMSTART 0x817a

#define ITRACE_DSP_EVENT_PMU_UDMA_DMLINK 0x817b

#define ITRACE_DSP_EVENT_PMU_UDMA_DMRESUME 0x817c

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_WR 0x817d

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_WR_MISS 0x817e

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_RD 0x817f

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_RD_MISS 0x8180

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_BYPASS_WR 0x8181

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_BYPASS_RD 0x8182

#define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_WR 0x8183

#define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_RD 0x8184

#define ITRACE_DSP_EVENT_PMU_UDMA_DLBC_FETCH 0x8185

#define ITRACE_DSP_EVENT_PMU_UDMA_DLBC_FETCH_CYCLES 0x8186

#define ITRACE_DSP_EVENT_PMU_UDMA_UNALIGNED_DESCRIPTOR 0x8187

#define ITRACE_DSP_EVENT_PMU_UDMA_ORDERING_DESCRIPTOR 0x8188

#define ITRACE_DSP_EVENT_PMU_UDMA_PADDING_DESCRIPTOR 0x8189

#define ITRACE_DSP_EVENT_PMU_UDMA_UNALIGNED_RD 0x818a

#define ITRACE_DSP_EVENT_PMU_UDMA_UNALIGNED_WR 0x818b

#define ITRACE_DSP_EVENT_PMU_UDMA_COHERENT_RD_CYCLES 0x818c

#define ITRACE_DSP_EVENT_PMU_UDMA_COHERENT_WR_CYCLES 0x818d

#define ITRACE_DSP_EVENT_PMU_UDMA_NONCOHERENT_RD_CYCLES 0x818e

#define ITRACE_DSP_EVENT_PMU_UDMA_NONCOHERENT_WR_CYCLES 0x818f

#define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_RD_CYCLES 0x8190

#define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_WR_CYCLES 0x8191

#define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_LOW 0x8192

#define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_HALF 0x8193

#define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_HIGH 0x8194

#define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_FULL 0x8195

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_VTCM_ACCESS 0x8196

#define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_VTCM_ACCESS 0x8197

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_VTCM_RD 0x8198

#define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_VTCM_RD 0x8199

#define ITRACE_DSP_EVENT_PMU_L2_UDMA_VTCM_CONGESTION 0x819a

#define ITRACE_DSP_EVENT_PMU_L2_AXIS_VTCM_CONGESTION 0x819b

#define ITRACE_DSP_EVENT_PMU_L2_AXI2_SLAVE_VTCM_CONGESTION 0x819c

#define ITRACE_DSP_EVENT_PMU_L2_MEMCPY_VTCM_CONGESTION 0x819d

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV0 0x819e

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV0 0x819f

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV1 0x81a0

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV1 0x81a1

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV2 0x81a2

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV2 0x81a3

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV3 0x81a4

#define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV3 0x81a5

#define ITRACE_DSP_EVENT_PMU_L2_PIPE_CONFLICT_STALL 0x81a6

#define ITRACE_DSP_EVENT_PMU_HMXCVT_BUF_FULL 0x81a7

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T6 0x81a8

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T7 0x81a9

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_7_THREAD_RUNNING 0x81aa

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_8_THREAD_RUNNING 0x81ab

#define ITRACE_DSP_EVENT_PMU_CYCLES_7_THREAD_RUNNING 0x81ac

#define ITRACE_DSP_EVENT_PMU_CYCLES_8_THREAD_RUNNING 0x81ad

#define ITRACE_DSP_EVENT_PMU_PST_USED_P0P1BUSY 0x81ae

#define ITRACE_DSP_EVENT_PMU_DU_STORE_BUFFER_COALESCED 0x81af

#define ITRACE_DSP_EVENT_PMU_PST_3STORETYPE_SBCONF_REPLAY 0x81b0

#define ITRACE_DSP_EVENT_PMU_PST_3LDST_L2FIFOCONF_REPLAY 0x81b1

#define ITRACE_DSP_EVENT_PMU_PST_STORE_SENTON_OTHPORT 0x81b2

#define ITRACE_DSP_EVENT_PMU_DU_STATE_REPLAY 0x81b3

#define ITRACE_DSP_EVENT_PMU_CYCLES_1_HVX_CONTEXTS_RUNNING 0x81b4

#define ITRACE_DSP_EVENT_PMU_CYCLES_2_HVX_CONTEXTS_RUNNING 0x81b5

#define ITRACE_DSP_EVENT_PMU_CYCLES_3_HVX_CONTEXTS_RUNNING 0x81b6

#define ITRACE_DSP_EVENT_PMU_CYCLES_4_HVX_CONTEXTS_RUNNING 0x81b7

#define ITRACE_DSP_EVENT_PMU_HMX_PKT_THREAD 0x81b8

#define ITRACE_DSP_EVENT_PMU_UDMA_DMPOLL 0x81b9

#define ITRACE_DSP_EVENT_PMU_UDMA_DMWAIT 0x81ba

#define ITRACE_DSP_EVENT_PMU_L2_CLEAN_CASTOUT 0x81bb

#define ITRACE_DSP_EVENT_PMU_AXI3_READ_REQUEST 0x81bc

#define ITRACE_DSP_EVENT_PMU_AXI3_LINE32_READ_REQUEST 0x81bd

#define ITRACE_DSP_EVENT_PMU_AXI3_WRITE_REQUEST 0x81be

#define ITRACE_DSP_EVENT_PMU_AXI3_LINE32_WRITE_REQUEST 0x81bf

#define ITRACE_DSP_EVENT_PMU_AXI3_RD_CONGESTION 0x81c0

#define ITRACE_DSP_EVENT_PMU_CYCLES_1_PACKET_COMMITTED 0x81c1

#define ITRACE_DSP_EVENT_PMU_CYCLES_2_PACKET_COMMITTED 0x81c2

#define ITRACE_DSP_EVENT_PMU_CYCLES_3_PACKET_COMMITTED 0x81c3

#define ITRACE_DSP_EVENT_PMU_CYCLES_4_PACKET_COMMITTED 0x81c4

#define ITRACE_DSP_EVENT_PMU_SMT_CLUSTER0 0x81c5

#define ITRACE_DSP_EVENT_PMU_SMT_CLUSTER1 0x81c6

#define ITRACE_DSP_EVENT_PMU_SMT_INTERCLUSTER 0x81c7

#define ITRACE_DSP_EVENT_PMU_SMT_CONFLICT_FOR_REG_READ_OR_CU_FWD 0x81c8

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_2_THREAD_RUNNING_2T_PLUS_0T 0x81c9

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_2_THREAD_RUNNING_1T_PLUS_1T 0x81ca

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_3_THREAD_RUNNING_3T_PLUS_0T 0x81cb

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_3_THREAD_RUNNING_2T_PLUS_1T 0x81cc

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING_4T_PLUS_0T 0x81cd

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING_3T_PLUS_1T 0x81ce

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING_2T_PLUS_2T 0x81cf

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_5_THREAD_RUNNING_4T_PLUS_1T 0x81d0

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_5_THREAD_RUNNING_3T_PLUS_2T 0x81d1

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_6_THREAD_RUNNING_4T_PLUS_2T 0x81d2

#define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_6_THREAD_RUNNING_3T_PLUS_3T 0x81d3

#define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS_PREFETCH_MISS 0x81d4

#define ITRACE_DSP_EVENT_PMU_SIMPLE_PACKET 0x81d5

#define ITRACE_DSP_EVENT_PMU_AXI3_LINE64_WRITE_REQUEST 0x81d6

#define ITRACE_DSP_EVENT_PMU_AXI3_LINE64_READ_REQUEST 0x81d7

#define ITRACE_DSP_EVENT_PMU_AXI3_WR_CONGESTION 0x81d8

#define ITRACE_DSP_EVENT_PMU_AXI3_INCOMPLETE_WRITE_REQUEST 0x81d9

#define ITRACE_DSP_EVENT_PMU_ICACHE_DATA_REPLAY 0x81da

#define ITRACE_DSP_EVENT_PMU_SMT_PKT_PICKED_BUT_NOT_COMMIT_PVIEW_CYCLES 0x81db

#define ITRACE_DSP_EVENT_PMU_SMT_PKT_IQ_NO_PKT_PVIEW_CYCLES 0x81dc

#define ITRACE_DSP_EVENT_PMU_SMT_PKT_NOT_SIMPLE_PVIEW_CYCLES 0x81dd

#define ITRACE_DSP_EVENT_PMU_SMT_PKT_NOT_READY_PVIEW_CYCLES 0x81de

#define ITRACE_DSP_EVENT_PMU_SMT_PKT_SLOT_CONFLICT_PVIEW_CYCLES 0x81df

#define ITRACE_DSP_EVENT_PMU_SMT_PKT_REG_FWD_BLOCK_PVIEW_CYCLES 0x81e0

#define ITRACE_DSP_EVENT_PMU_CLADE2_EB_FULL 0x81e1

#define ITRACE_DSP_EVENT_PMU_CLADE2_RD_REQ 0x81e2

#define ITRACE_DSP_EVENT_PMU_CLADE2_RDCACHE_MISS 0x81e3

#define ITRACE_DSP_EVENT_PMU_CLADE2_WR_REQ 0x81e4

#define ITRACE_DSP_EVENT_PMU_CLADE2_WRCACHE_MISS 0x81e5

#define ITRACE_DSP_EVENT_PMU_AXI_EWD_REQUEST 0x81e6

#define ITRACE_DSP_EVENT_PMU_AXI_EWD_REQUEST_EVEN 0x81e7

#define ITRACE_DSP_EVENT_PMU_AXI_CMO_REQUEST 0x81e8

#define ITRACE_DSP_EVENT_PMU_AXI_CMO_REQUEST_EVEN 0x81e9

#define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS_PREFETCH_MISS_IU0 0x81ea

#define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS_PREFETCH_MISS_IU1 0x81eb

#define ITRACE_DSP_EVENT_PMU_VMEM_ST_SMT_DU_PORT_CONFLICT_REPLAY 0x81ec

#define ITRACE_DSP_EVENT_PMU_DU_SPF_DTLBPGCROSS 0x81ed

#define ITRACE_DSP_EVENT_PMU_DU_SPF_DCACHE_HIT 0x81ee

#define ITRACE_DSP_EVENT_PMU_DU_SPF_DCACHE_MISS 0x81ef

#define ITRACE_DSP_EVENT_PMU_DU_SPF_L2FIFOFULL_RETRY 0x81f0

#define ITRACE_DSP_EVENT_PMU_DU_SPF_L2BUFFULL_RETRY 0x81f1

#define ITRACE_DSP_EVENT_PMU_DU_SPF_CONFLICT_RETRY 0x81f2

#define ITRACE_DSP_EVENT_PMU_DU_NUM_WAY_PREDICTIONS 0x81f3

#define ITRACE_DSP_EVENT_PMU_DU_WAY_PRED_REPLAYS 0x81f4

#define ITRACE_DSP_EVENT_PMU_DU_BANKCONFLICTREPLAY_INVALID 0x81f5

#define ITRACE_DSP_EVENT_PMU_L2_IU_BRANCH_CACHE_WRITE_REQUEST 0x81f6

#define ITRACE_DSP_EVENT_PMU_L2_IU_BRANCH_CACHE_WRITE 0x81f7

#define ITRACE_DSP_EVENT_PMU_THREAD_IDLE_PVIEW_CYCLES 0x81f8

#define ITRACE_DSP_EVENT_PMU_DU_CONFLICT_PVIEW_CYCLES 0x81f9

#define ITRACE_DSP_EVENT_PMU_HVX_VFIFO_EMPTY 0x81fa

#define ITRACE_DSP_EVENT_PMU_HMX_CLK 0x81fb

#define ITRACE_DSP_EVENT_PMU_HMX_MXFIFO_EMPTY 0x81fc

#define ITRACE_DSP_EVENT_PMU_TAGE_TABLE_ALLOC 0x81fd

#define ITRACE_DSP_EVENT_PMU_TAGE_TABLE_HIT 0x81fe

#define ITRACE_DSP_EVENT_PMU_TAGE_BRANCH_OVERRIDE 0x81ff

#define ITRACE_DSP_EVENT_PMU_DPM_AVG_COMPRESSED 0x8200

#define DUMMY_DSP_PMU_EVENT_LAST 0x8201


#define ITRACE_NUMBER_DEFINED_DSP_EVENTS_PMU (DUMMY_DSP_PMU_EVENT_FIRST&DUMMY_DSP_PMU_EVENT_LAST)

#define ITRACE_DSP_PMU_OFFSET (DUMMY_DSP_PMU_EVENT_FIRST+1)

#define ITRACE_DSP_IS_PMU_EVENT(id) ((id>=ITRACE_DSP_PMU_OFFSET) && (id<(ITRACE_DSP_PMU_OFFSET+ITRACE_NUMBER_DEFINED_DSP_EVENTS_PMU)))

// Undocumented. Used by multi-pass macros

#ifdef __cplusplus
extern "C" {
#endif
int get_dsp_idx_from_version_number(int dsp_version);
int get_pmu_event_code_from_id(int id, int dsp_idx);
int get_pmu_event_id_from_name(const char* name);
#ifdef __cplusplus
}
#endif
#endif