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itrace
Instrumented Trace
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itrace
Instrumented Trace
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| #define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_VTCM_ACCESS 0x8197 |
AXI2 Slave access to VTCM. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_VTCM_RD 0x8199 |
AXI2 Slave rd access to VTCM. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_INCOMPLETE_WRITE_REQUEST 0x81d9 |
L2 line-sized write was made to the AXI3 master, but not all bytes were valid. Includes segmented writes. Excludes WT stores. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_LINE32_READ_REQUEST 0x81bd |
Number of 32-byte line read requests issued by the tertiary AXI master. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_LINE32_WRITE_REQUEST 0x81bf |
Number of 32-byte line write requests issued by the tertiary AXI master. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_LINE64_READ_REQUEST 0x81d7 |
Number of 64-byte line read requests issued by the primary AXI3 master. Includes all interleaved requests Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_LINE64_WRITE_REQUEST 0x81d6 |
Number of 64-byte line write requests issued by the primary AXI3 master. Includes all interleaved requests. All bytes are valid. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_RD_CONGESTION 0x81c0 |
Tertiary AXI read command queue is full, and an operation is stuck at the head of the primary AXI master command queue. Includes all interleaved requests. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_READ_REQUEST 0x81bc |
All read requests issued by the tertiary AXI master. Includes full lines and partial lines. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_WR_CONGESTION 0x81d8 |
Tertiary AXI write command or data queue is full, and an operation is stuck at the head of the primary AXI3 master command queue. Includes all interleaved requests. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI3_WRITE_REQUEST 0x81be |
All write requests issued by the tertiary AXI master. Includes full lines and partial lines. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_CMO_REQUEST 0x81e8 |
Cache maintenance operation request from the QDSP6 core to AXIM. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_CMO_REQUEST_EVEN 0x81e9 |
Cache maintenance operation request from the QDSP6 core to AXIM Interleave0. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_EWD_REQUEST 0x81e6 |
L2 cache eviction of clean data to the AXI master bus. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_EWD_REQUEST_EVEN 0x81e7 |
L2 cache eviction of clean data to the even interleaved AXI master bus. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_INCOMPLETE_WRITE_REQUEST_EVEN 0x810e |
L2 line-sized write was made to the even-interleaved AXI master, but not all bytes were valid. Includes segmented writes. Excludes WT stores. This event captures the number of writes coalesced at a line level. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE128_READ_REQUEST 0x80d7 |
Number of 128-byte line read requests issued by the primary AXI master. Includes all interleaved requests. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE128_READ_REQUEST_EVEN 0x8105 |
Number of 128-byte line read requests issued by the even interleaved AXI master. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE128_WRITE_REQUEST 0x80d8 |
Number of 128-byte line write requests issued by the primary AXI master. Includes all interleaved requests. All bytes are valid. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE128_WRITE_REQUEST_EVEN 0x810a |
Number of 128-byte line write requests issued by the even-interleaved AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE256_READ_REQUEST 0x8104 |
Number of 256-byte line read requests issued by the AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE256_READ_REQUEST_EVEN 0x810f |
Number of 256-byte line read requests issued by an even-interleaved AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE256_WRITE_REQUEST 0x80f8 |
Number of 256-byte line write requests issued by the AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE256_WRITE_REQUEST_EVEN 0x8110 |
Number of 256-byte line write requests issued by an even-interleaved AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE32_READ_REQUEST_EVEN 0x8107 |
Number of 32-byte line read requests issued by the even-interleaved AXI master. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE32_WRITE_REQUEST_EVEN 0x8109 |
Number of 32-byte line write requests issued by the even-interleaved AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE64_READ_REQUEST_EVEN 0x810b |
Number of 64-byte line read requests issued by the even-interleaved AXI master. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE64_WRITE_REQUEST_EVEN 0x810c |
Number of 64-byte line write requests issued by the even-interleaved AXI master. All bytes are valid. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_READ_REQUEST_EVEN 0x8106 |
All read requests issued by the even interleaved AXI master. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV0 0x819e |
AXI slave multi-beat access for vtcm interleave 0. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV1 0x81a0 |
AXI slave multi-beat access for vtcm interleave 1. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV2 0x81a2 |
AXI slave multi-beat access for vtcm interleave 2. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS_ILV3 0x81a4 |
AXI slave multi-beat access for vtcm interleave 3. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV0 0x819f |
AXI slave single-beat access for vtcm interleave 0. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV1 0x81a1 |
AXI slave single-beat access for vtcm interleave 1. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV2 0x81a3 |
AXI slave single-beat access for vtcm interleave 2. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS_ILV3 0x81a5 |
AXI slave single-beat access for vtcm interleave 3. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_VTCM_ACCESS 0x8196 |
AXI Slave Access to VTCM. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_VTCM_RD 0x8198 |
AXI Slave read access to VTCM. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_WR_CONGESTION_EVEN 0x810d |
Even-interleaved AXI write command or data queue is full, and an operation is stuck at the head of the even interleaved AXI master command queue. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_WRITE_REQUEST_EVEN 0x8108 |
All write requests issued by the even-interleaved AXI master. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE2_EB_FULL 0x81e1 |
CLADE2 can use up to two eviction buffer entries. Indicates that both entries are used and CLADE2 is congested. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE2_RD_REQ 0x81e2 |
Number of L2 cache read requests in the CLADE2 region. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE2_RDCACHE_MISS 0x81e3 |
Number of L2 cache read request misses in the CLADE2 region. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE2_WR_REQ 0x81e4 |
Number of L2 cache write requests in the CLADE2 region. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE2_WRCACHE_MISS 0x81e5 |
Number of L2 cache write request misses in the CLADE2 region. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_NOPS 0x80f4 |
Number of committed NOPs. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_2_THREAD_RUNNING_1T_PLUS_1T 0x81ca |
Number of committed packets with two threads running on the different cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_2_THREAD_RUNNING_2T_PLUS_0T 0x81c9 |
Number of committed packets with two threads running on the same cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_3_THREAD_RUNNING_2T_PLUS_1T 0x81cc |
Number of committed packets with three threads running, two threads on one cluster and 1 on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_3_THREAD_RUNNING_3T_PLUS_0T 0x81cb |
Number of committed packets with three threads running on the same cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING_2T_PLUS_2T 0x81cf |
Number of committed packets with four threads running, two threads on one cluster and two threads running on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING_3T_PLUS_1T 0x81ce |
Number of committed packets with four threads running, three threads on one cluster and one thread running on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING_4T_PLUS_0T 0x81cd |
Number of committed packets with four threads running on same cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_5_THREAD_RUNNING 0x80ef |
Number of committed packets with five threads running. Running means the threads are not in Wait or Stop mode. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_5_THREAD_RUNNING_3T_PLUS_2T 0x81d1 |
Number of committed packets with 5 threads running, three threads on one cluster and two threads running on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_5_THREAD_RUNNING_4T_PLUS_1T 0x81d0 |
Number of committed packets with 5 threads running, four threads on one cluster and one thread running on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_6_THREAD_RUNNING 0x80f0 |
Number of committed packets with six threads running. Running means the threads are not in Wait or Stop mode. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_6_THREAD_RUNNING_3T_PLUS_3T 0x81d3 |
Number of committed packets with six threads running, three threads on one cluster and three threads running on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_6_THREAD_RUNNING_4T_PLUS_2T 0x81d2 |
Number of committed packets with six threads running, four threads on one cluster and two threads running on another cluster. Running means the threads are not in the Wait or Stop state. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_7_THREAD_RUNNING 0x81aa |
Number of committed packets with seven threads running. Running means the threads are not in Wait or Stop mode. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_8_THREAD_RUNNING 0x81ab |
Number of committed packets with eight threads running. Running means the threads are not in Wait or Stop mode. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T0 0x80e9 |
Number of packets that are committed by thread 0. Packets are executed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T1 0x80ea |
Number of packets that are committed by thread 1. Packets are executed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T2 0x80eb |
Number of packets that are committed by thread 2. Packets are executed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T3 0x80ec |
Number of packets that are committed by thread 3. Packets are executed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T4 0x80ed |
Number of packets that are committed by thread 4. Packets are executed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T5 0x80ee |
Number of packets that are committed by thread 5. Packets are executed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T6 0x81a8 |
Thread 6 committed a packet. Packets are executed. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_T7 0x81a9 |
Thread 7 committed a packet. Packets are executed. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC0_AXISLAVE_ACCESS 0x80bc |
Coprocessor memory accessed by AXI slave. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_CYCLES_RUNNING 0x80c1 |
Cycles with at least one thread running that has its XE bit set and XA is pointing to Silver context 0. Should NOT include threads that either in WAIT mode or OFF mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC0_FIFO_DISPATCH 0x80c0 |
Total enqueues into coprocessor queue, includes vector instructions and scalar L1S accesses. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_FIFO_FULL_REPLAY 0x80bb |
Core replays due to unforseen VFIFO full conditions. Supported architectures: V65
| #define ITRACE_DSP_EVENT_PMU_COPROC0_FIFO_FULL_STALL 0x80e1 |
Number of cycles any thread had to stall due to VFIFO full for Silver context 0. This does not include cycles needed by CU to schedule the next packet after DU is out of VFIFO full stall. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC0_IDLE 0x80ba |
Cycles where coprocessor was idle. No instructions in coprocessor queue or pipeline. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_IU_L1S_REQUEST 0x80e3 |
IU Fetch from L1S Supported architectures: V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_IU_REPLAY 0x80e2 |
Replay due to IU request Supported architectures: V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_MNOC_AXI_REPLAY 0x80c3 |
Replay due to MNOC access, AXI access, or L1S scalar load return busy Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_1_VEXTRACT 0x80be |
Committed packet with 1 vextract instruction. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_1_VMEM 0x80b7 |
Committed packet with 1 silver VMEM instruction Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_2_VEXTRACT 0x80bf |
Committed packet with 2 vextract instruction. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_2_VMEM 0x80b8 |
Committed packet with 2 silver VMEM instructions Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_EXEC 0x80b6 |
Committed packets on the coprocessor thread executed in coprocessor. Includes scalar stores to L1S but not scalar loads to L1S. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_REG_INTERLOCK_REPLAY 0x80c2 |
Replay due to register interlock Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_REPLAY 0x80b9 |
Coprocessor had an internal replay. Includes register interlock replay, AXIslave access stalled, return FIFO full replay. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_RFIFO_REPLAY 0x80c4 |
Replay due to RFIFO Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC0_VEXTRACT_STALL 0x80bd |
Total cycles any thread is stalled for vextract data return from Silver context 0. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC1_CYCLES_RUNNING 0x80d0 |
Cycles with at least one thread running that has its XE bit set and XA is pointing to Silver context 1. Should NOT include threads that either in WAIT mode or OFF mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC1_FIFO_DISPATCH 0x80cf |
Total enqueues into coprocessor queue, includes vector instructions and scalar L1S accesses. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_FIFO_FULL_REPLAY 0x80cb |
Core replays due to unforseen VFIFO full conditions. Supported architectures: V65
| #define ITRACE_DSP_EVENT_PMU_COPROC1_FIFO_FULL_STALL 0x80e4 |
Number of cycles any thread had to stall due to VFIFO full for Silver context 1. This does not include cycles needed by CU to schedule the next packet after DU is out of VFIFO full stall. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC1_IDLE 0x80ca |
Cycles where coprocessor was idle. No instructions in coprocessor queue or pipeline. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_MNOC_AXI_REPLAY 0x80e5 |
Replay due to MNOC access, AXI access, or L1S scalar load return busy Supported architectures: V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_1_VEXTRACT 0x80cd |
Committed packet with 1 vextract instruction. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_1_VMEM 0x80c7 |
Committed packet with 1 silver VMEM instruction Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_2_VEXTRACT 0x80ce |
Committed packet with 2 vextract instruction. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_2_VMEM 0x80c8 |
Committed packet with 2 silver VMEM instructions Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_EXEC 0x80c6 |
Committed packets on the coprocessor thread executed in coprocessor. Includes scalar stores to L1S but not scalar loads to L1S. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_PKT_XE 0x80c5 |
Committed packets on any thread with the XE bit set and XA pointing to Silver context 1. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC1_REG_INTERLOCK_REPLAY 0x80d1 |
Replay due to register interlock Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_REPLAY 0x80c9 |
Coprocessor had an internal replay. Includes register interlock replay, AXIslave access stalled, return FIFO full replay. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_RFIFO_REPLAY 0x80e6 |
Replay due to RFIFO Supported architectures: V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC1_VEXTRACT_STALL 0x80cc |
Total cycles any thread is stalled for vextract data return from Silver context 1. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC2_CYCLES_RUNNING 0x8138 |
Cycles with at least one thread running that has its XE bit set and XA is pointing to Silver context 2. Should NOT include threads that either in WAIT mode or OFF mode. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC2_FIFO_DISPATCH 0x8137 |
Total enqueues into coprocessor queue, includes vector instructions and scalar L1S accesses. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_FIFO_FULL_STALL 0x8133 |
Number of cycles any thread had to stall due to VFIFO full for Silver context 2. This does not include cycles needed by CU to schedule the next packet after DU is out of VFIFO full stall. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC2_IDLE 0x8132 |
Cycles where coprocessor was idle. No instructions in coprocessor queue or pipeline. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_MNOC_AXI_REPLAY 0x813a |
Replay due to MNOC access, AXI access, or L1S scalar load return busy Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_1_VEXTRACT 0x8135 |
Committed packet with 1 vextract instruction. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_1_VMEM 0x812f |
Committed packet with 1 silver VMEM instruction Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_2_VEXTRACT 0x8136 |
Committed packet with 2 vextract instruction. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_2_VMEM 0x8130 |
Committed packet with 2 silver VMEM instructions Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_EXEC 0x812e |
Committed packets on the coprocessor thread executed in coprocessor. Includes scalar stores to L1S but not scalar loads to L1S. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_PKT_XE 0x812d |
Committed packets on any thread with the XE bit set and XA pointing to Silver context 2. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC2_REG_INTERLOCK_REPLAY 0x8139 |
Replay due to register interlock Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_REPLAY 0x8131 |
Coprocessor had an internal replay. Includes register interlock replay, AXIslave access stalled, return FIFO full replay. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_RFIFO_REPLAY 0x813b |
Replay due to RFIFO Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC2_VEXTRACT_STALL 0x8134 |
Total cycles any thread is stalled for vextract data return from Silver context 2. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC3_CYCLES_RUNNING 0x8147 |
Cycles with at least one thread running that has its XE bit set and XA is pointing to Silver context 3. Should NOT include threads that either in WAIT mode or OFF mode. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC3_FIFO_DISPATCH 0x8146 |
Total enqueues into coprocessor queue, includes vector instructions and scalar L1S accesses. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_FIFO_FULL_STALL 0x8142 |
Number of cycles any thread had to stall due to VFIFO full for Silver context 3. This does not include cycles needed by CU to schedule the next packet after DU is out of VFIFO full stall. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC3_IDLE 0x8141 |
Cycles where coprocessor was idle. No instructions in coprocessor queue or pipeline. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_MNOC_AXI_REPLAY 0x8149 |
Replay due to MNOC access, AXI access, or L1S scalar load return busy Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_1_VEXTRACT 0x8144 |
Committed packet with 1 vextract instruction. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_1_VMEM 0x813e |
Committed packet with 1 silver VMEM instruction Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_2_VEXTRACT 0x8145 |
Committed packet with 2 vextract instruction. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_2_VMEM 0x813f |
Committed packet with 2 silver VMEM instructions Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_EXEC 0x813d |
Committed packets on the coprocessor thread executed in coprocessor. Includes scalar stores to L1S but not scalar loads to L1S. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_PKT_XE 0x813c |
Committed packets on any thread with the XE bit set and XA pointing to Silver context 3. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC3_REG_INTERLOCK_REPLAY 0x8148 |
Replay due to register interlock Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_REPLAY 0x8140 |
Coprocessor had an internal replay. Includes register interlock replay, AXIslave access stalled, return FIFO full replay. Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_RFIFO_REPLAY 0x814a |
Replay due to RFIFO Supported architectures: V68 V69
| #define ITRACE_DSP_EVENT_PMU_COPROC3_VEXTRACT_STALL 0x8143 |
Total cycles any thread is stalled for vextract data return from Silver context 3. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC_ACTIVE 0x8093 |
VXU clocked/non-idle Supported architectures: V65
| #define ITRACE_DSP_EVENT_PMU_COPROC_BUSY_PVIEW_CYCLES 0x80de |
Cycles cluster cannot commit because the coprocessor is busy. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC_ENABLED 0x8094 |
VXU enabled and powered Supported architectures: V65
| #define ITRACE_DSP_EVENT_PMU_CU_REDISPATCH 0x8091 |
Any case where a packet is redispatched. Most commonly, HVX FIFO becomes full while an HVX packet is in flight. It can also be a replay requested for a non-replayable instruction, or a forwarding bus resource conflict. Supported architectures: V65 V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_CYCLES_1_HVX_CONTEXTS_RUNNING 0x81b4 |
Cycles 1 HVX context running Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_1_PACKET_COMMITTED 0x81c1 |
Number of cycles when one packet is committed. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_2_HVX_CONTEXTS_RUNNING 0x81b5 |
Cycles 2 HVX contexts running concurrently Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_2_PACKET_COMMITTED 0x81c2 |
Number of cycles when two packets are committed. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_3_COPROC_THREADS_ONE_CLUSTER 0x8111 |
Number of processor cycles during which a cluster has three threads in Run mode with the coprocessor bit (SSR.XE) enabled. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_3_HVX_CONTEXTS_RUNNING 0x81b6 |
Cycles 3 HVX contexts running concurrently Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_3_PACKET_COMMITTED 0x81c3 |
Number of cycles when three packets are committed. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_4_HVX_CONTEXTS_RUNNING 0x81b7 |
Cycles 4 HVX contexts running concurrently Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_4_PACKET_COMMITTED 0x81c4 |
Number of cycles when four packets are committed. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_5_THREAD_RUNNING 0x80e7 |
Processor cycles that exactly five threads are running. Running means the threads are not in the Wait or Stop state. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_6_THREAD_RUNNING 0x80e8 |
Processor cycles that exactly six threads are running. Running means the threads are not in the Wait or Stop state. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_7_THREAD_RUNNING 0x81ac |
Processor cycles that exactly seven threads are running. Running means the threads are not in Wait or Stop mode. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_8_THREAD_RUNNING 0x81ad |
Processor cycles that exactly eight threads are running. Running means the threads are not in Wait or Stop mode. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCACHE_EVICTION_IN_PIPE_REPLAY 0x8101 |
Number of replays taken by a packet because an eviction in progress is occupying the pipe. Supported architectures: V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_DISPATCHED_INSTS 0x80f7 |
Number of instructions that the CU dispatched. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DISPATCHED_PACKETS 0x80f6 |
Number of packets that the CU dispatched. NOPs instructions are squashed. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DPM_AVG_COMPRESSED 0x8200 |
representation of relative DPM value(obtained using the DPM weights) produced every cycle. Computed absolute average power (mW) = (DPM_AVG_COMPRESSED count * max DPM value from DPM Weights * scaling factor)/execution time(ns) Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_DU_BANKCONFLICTREPLAY_INVALID 0x81f5 |
Number of time bank conflict replay was prevented due to way prediction Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_DU_CONFLICT_PVIEW_CYCLES 0x81f9 |
Cycles cluster cannot commit due to a DU resource conflict. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_DU_DEALLOC_SECURITY_REPLAY 0x8097 |
Replays due to executing deallocframe or dealloc_return with FRAMEKEY != 0. Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_DU_L1S_LOAD_ACCESS 0x80db |
Number of scalar load accesses to L1S. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_NUM_WAY_PREDICTIONS 0x81f3 |
Number of times DU did way predictions for loads Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_DU_SECMISS_REPLAY 0x8096 |
A load hits on a reserved line while a fill is pending. Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_DU_SPF_CONFLICT_RETRY 0x81f2 |
Number of cycles that prefetches losing arbitration Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_SPF_DCACHE_HIT 0x81ee |
Number of prefetch requests hitting in L1D$ Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_SPF_DCACHE_MISS 0x81ef |
Number of prefetch requests missing in L1D$ Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_SPF_DTLBPGCROSS 0x81ed |
Number of stopping prefetching due to page cross Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_SPF_L2BUFFULL_RETRY 0x81f1 |
Number of prefetch retry on L2 credits/AQoS busy Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_SPF_L2FIFOFULL_RETRY 0x81f0 |
Number of prefetch retry on L2FIFO queue full Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_STATE_REPLAY 0x81b3 |
Number of times an access replayed because the access one cycle ahead of it was allocating or invalidating a way in the same index. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_STORE_BUFFER_COALESCED 0x81af |
Number of times an incoming store was coalesced into an existing valid store buffer entry. Each valid store buffer entry is dword-aligned. Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_DU_STORE_LINK 0x80da |
Store that is linked to an earlier request to the same location. Supported architectures: V66 V68 V69
| #define ITRACE_DSP_EVENT_PMU_DU_STORE_RELEASE_CREDIT_STALL 0x8103 |
Stall occurs because there are not enough credits from the store release. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_WAY_PRED_REPLAYS 0x81f4 |
Number of times DU replayed due to way misprediction Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_GLOBAL_POWERLIMITS_OVER 0x80f3 |
Sustained global power that exceeds the overall global limits management threshold and limits the budget threshold. Causes the thread-specific LMH to engage. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_GUARDBUF_SETMATCH_CRACKING_REPLAY 0x8100 |
Number of replays taken by a younger access due to an index match with a guard buffer entry. If the younger access hits in D$, only the guard buffer entry of the other thread is checked. Otherwise, an index match with either thread's guard buffer entry will result in this replay. Supported architectures: V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_HMX_ACTIVE 0x814b |
HMX Active (mxfifo, mac, or cvt not empty) Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_CLK 0x81fb |
number of cycles hmx is active with respective to hmx clock Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_HMX_CVT 0x814f |
Bias load, store, or convert issue. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_CVT_FULL 0x814c |
Convert fifo full. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_DROP 0x814e |
HMX malformed packet that is dropped or accumulator swap. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_MAC 0x8150 |
Multiply issue. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_MAC_FULL 0x814d |
Multiply fifo full. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_MXFIFO_EMPTY 0x81fc |
Number of cycles a thread has empty hmx fifo Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_HMX_MXFIFO_FULL 0x8151 |
Core could not issue due to MXFIFO full. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMX_PKT_THREAD 0x81b8 |
Packets committed with XE2 bit set Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXARRAY_FLT_ACC 0x816d |
Number of active HMX floating-point accumulates. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXARRAY_FLT_CVT 0x816f |
Number of active HMX floating-point converts. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXARRAY_FLT_MPY 0x816b |
Number of active HMX floating-point multiplies. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXARRAY_FXP_ACC 0x816c |
Number of active HMX fixed-point accumulates. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXARRAY_FXP_CVT 0x816e |
Number of active HMX fixed-point converts. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXARRAY_FXP_MPY 0x816a |
Number of active HMX fixed-point multiplies. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_BUF_FULL 0x81a7 |
Wait on convert intermediate buffer full. Supported architectures: V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_BUSY 0x815e |
Older Convert in pipeline needs to finish. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_CLR 0x8169 |
Clear issued. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_FLT 0x8167 |
Final accumulator read from floating-point array. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_FLT_PARTIAL 0x8164 |
Accumulator read from floating-point array. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_FXP 0x8166 |
Final accumulator read from fixed-point array. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_FXP_PARTIAL 0x8163 |
Accumulator read from fixed-point array. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_LD 0x8165 |
Bias load issued. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_LD_OUTSTANDING 0x815f |
Stall on scale/bias to load. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_ORDER 0x815d |
Oldert MAC using the same accumulator not finished. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_POWER_OVER 0x8162 |
Estimated voltage undershoot exceeding a threshold. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_ST 0x8168 |
Bias store issued. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_VOLTAGE_UNDER 0x8161 |
Estimated voltage undershoot exceeding a threshold. Supported architectures: V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_HMXCVT_WR_FULL 0x8160 |
Stall on write buffer full. Supported architectures: V68
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_ACT_OUTSTANDING 0x8153 |
Activation not ready. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_DRAIN 0x815c |
Final dummy cycle to drain activation or weight. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_DRAIN_PARTIAL 0x8159 |
Dummy cycle to drain activation or weight. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_FLT 0x815b |
Final floating-point mac issue cycle. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_FLT_PARTIAL 0x8158 |
Floating-point mac issue cycle. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_FULL 0x8152 |
Downstream umac fifo full. Supported architectures: V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_FXP 0x815a |
Final fixed-point mac issue cycle. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_FXP_PARTIAL 0x8157 |
Fixed-point mac issue cycle. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_MULT_DROP 0x8155 |
MAC exceeded maximum multiplies. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_POWER_OVER 0x8156 |
Measured or estimated power has exceeded a limit. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HMXMAC_WGT_OUTSTANDING 0x8154 |
Weight not ready. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_ACC_ORDER 0x8112 |
Stall cycles due to accumulator not produced in previous context cycle. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_CORE_VFIFO_FULL_STALL 0x80ae |
Number of cycles a thread had to stall due to VFIFO Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_EMPTY 0x809c |
VFIFO empty Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_L2_LOAD_ACCESS 0x80b1 |
L2 cacheable load access from HVX. Any load access from HVX that may cause a lookup in the L2 cache. Excludes cache ops, uncacheables, scalars Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_L2_LOAD_MISS 0x80b2 |
L2 cacheable miss from HVX. Of the events qualified by 0xFB, the ones that resulted in a miss i.e. the 64-byte address was not previously allocated in the L2 tag array and data will be fetched from backing memory Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_L2_LOAD_SECONDARY_MISS 0x80b3 |
Of the events in 0xFB, the ones where the load could not be returned due to the immediatately prior access for the line being a pending load or pending L2Fetch Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_L2_STORE_ACCESS 0x80af |
L2 cacheable store access from HVX. Any store access from HVX that may cause a lookup in the L2 cache. Excludes cache ops, uncacheables, scalar stores Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_L2_STORE_MISS 0x80b0 |
L2 cacheable miss from HVX. Of the events qualified by 0xF9, the ones that resulted in a miss. Specifically the cases where the 64-byte-line address is not in the tag or a coalesce buffer. DCZero does not count as a miss, if it allocates without a backing store fetch Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_LD_L2_OUTSTANDING 0x80a0 |
Stall cycles due to load pending Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_LD_VTCM_OUTSTANDING 0x809f |
Increments by 2 per cycle in 128-byte mode. Stall cycles due to vtcm load pending Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_OTHER_PART_OUTSTANDING 0x80a8 |
Other part of the packet in another context not ready in 128 Byte mode Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_PARTIAL_PKT 0x80ab |
Increments by 2 per cycle in 128-byte mode. Stall cycles due to multi-issue packet Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_PKT 0x80ac |
Increments by 2 per packet in 128-byte mode. Packets with HVX instructions Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_PKT_PARTIAL 0x8118 |
Stall cycles due to multi-issue packet Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_PKT_THREAD 0x80ad |
Committed packets on a thread with the XE bit set, whether executed in Q6 or coprocessor Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_POWER_OVER 0x80aa |
Throttling: Sustained power exceeds budget Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_REG_ORDER 0x809e |
Stall cycles due to interlocks Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_FULL 0x8114 |
Scatter/gather: Network scoreboard not updated Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_IN_FULL 0x8115 |
scatter/gather input buffer full Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_OUTSTANDING 0x80a3 |
Scatter/gather: Network scoreboard not updated Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_SCATGATH_SHARED_FULL 0x80a4 |
scatter/gather input buffer full Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_ST_DWR_BANK_CONFLICT 0x80e0 |
Store stall due to a DMA WR bank conflict Supported architectures: V66
| #define ITRACE_DSP_EVENT_PMU_HVX_ST_FULL 0x8116 |
store buffer full Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_ST_L2_OUTSTANDING 0x80a2 |
Stall cycles due to store not yet allocated in L2 Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_ST_L2_SHARED_FULL 0x80a5 |
Increments by 2 per cycle in 128-byte mode. Insufficient space for data return to L2 Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_ST_ST_BANK_CONFLICT 0x80a6 |
VFIFO stall due to VTCM ST bank conflict with ST Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_ST_VTCM_OUTSTANDING 0x80a1 |
Increments by 2 per cycle in 128-byte mode. Stall cycles due to store not yet allocated in L2 Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_TCM_LOAD_ACCESS 0x80b5 |
TCM load access for HVX. HVX load from the L2 tcm space Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_TCM_STORE_ACCESS 0x80b4 |
TCM store access for HVX. HVX store to the L2 tcm space Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_VFIFO_EMPTY 0x81fa |
Number of cycles a thread had empty VFIFO Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_HVX_VOLTAGE_UNDER 0x80a9 |
Throttling: Voltage model would exceed undershoot threshold Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_VOLTAGE_VIRUS_OVER 0x8117 |
Throttling: Voltage virus overshoot Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_VTCM_BANDWIDTH_OVER 0x80a7 |
Bank Bandwidth exceeded Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_VTCM_OUTSTANDING 0x8113 |
Stall cycles due to VTCM transaction pending. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_WAIT 0x809d |
Pipeline reserved by another context Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVX_WAIT_EMPTY 0x809b |
waiting context, qualified with cross-context VFIFO active Supported architectures: V65 V66
| #define ITRACE_DSP_EVENT_PMU_HVXLD_L2 0x8119 |
L2 cacheable load access from HVX. Any load access from HVX that may cause a lookup in the L2 cache. Excludes cache ops, uncacheables, scalars Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXLD_L2_MISS 0x811b |
L2 cacheable miss from HVX. Of the events qualified by 0xFB, the ones that resulted in a miss i.e. the 64-byte address was not previously allocated in the L2 tag array and data will be fetched from backing memory Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXLD_L2_SECONDARY_MISS 0x811c |
Of the events in 0xFB, the ones where the load could not be returned due to the immediatately prior access for the line being a pending load or pending L2Fetch Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXLD_L2_TCM 0x811a |
TCM load access for HVX. HVX load from the L2 tcm space Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXPIPE_ALU 0x8129 |
Executed simple ALU instruction Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXPIPE_MPY 0x812a |
Executed multiply or abs-diff instruction Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXPIPE_PERM 0x812c |
Executed permute or cross-lane data movement instruction Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXPIPE_SHIFT 0x812b |
Executed bit shift or bit count instruction Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2 0x8124 |
Vector store to L2. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2_CONFLICT 0x8120 |
Lost against another partition write to FIFO for L2 interleave. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2_FULL 0x8122 |
write fifo full. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2_MISS 0x8125 |
L2 cacheable miss from HVX store. Specifically the cases where the 128-byte-line address is not in the tag or a coalesce buffer. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2_SECODARY_MISS 0x8128 |
L2 cacheable secondary miss from HVX store. Specifically the cases where the 128-byte-line address is not in the tag or a coalesce buffer. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2_WR 0x811d |
Vector write in L2. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_L2TCM 0x8126 |
TCM store access for HVX. HVX store to the L2 tcm space Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_SLD_CONFLICT 0x811e |
Lower priority with respect to scalar load to access L2 return data bus Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_VTCM 0x8127 |
Vector store to VTCM. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_VTCM_CONFLICT 0x8121 |
Lost against another partition write to FIFO for VTCM interleave. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_VTCM_FULL 0x8123 |
write fifo full. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVXST_VTCM_GATH_CONFLICT 0x811f |
Lower priority with respect to gather Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ICACHE_DATA_REPLAY 0x81da |
Number of I-cache data replays due to incorrect way predictions. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS_PREFETCH_MISS 0x81d4 |
Number of iprfetches initiated on demand misses. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS_PREFETCH_MISS_IU0 0x81ea |
Number of iprfetches initiated on a demand miss in IU0. Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS_PREFETCH_MISS_IU1 0x81eb |
Number of iprfetches initiated on a demand miss in IU1. Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_ISSUED_INSTS 0x80f5 |
Speculatively issued instructions delivered from the IU. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_L1S_ACCESS 0x80d2 |
Number of IU L1S loads. Includes demands or prefetches. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_L1S_AXIS_STALL 0x80d4 |
Number of IU L1S stalls due to an AXI slave. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_L1S_NO_GRANT 0x80d5 |
IU request to L1S, and no grant from the vector unit. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_L1S_PREFETCH 0x80d3 |
Number of IU L1S prefetches. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_AXI2_SLAVE_VTCM_CONGESTION 0x819c |
VTCM access from secondary AXI slave cannot make progress due to conflicts with VTCM accesses from other sources or credits are all taken. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_AXIS_VTCM_CONGESTION 0x819b |
VTCM access from primary AXI slave cannot make progress due to conflicts with VTCM accesses from other sources or credits are all taken. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_CLEAN_CASTOUT 0x81bb |
Number of clean line evictions from L2 cache. Triggers when L2 cache evicts a line due to an allocation. Not triggered on cache operations. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_BRANCH_CACHE_WRITE 0x81f7 |
Number of writes to the bimodal bits of instructions in the L2 cache. This event is the number of event 122 requests that completed by updating memory in the L2 cache or TCM. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_BRANCH_CACHE_WRITE_REQUEST 0x81f6 |
Number of requests sent from the IU to the L2 cache to write the bimodal bits of instructions in L2. Includes all requests, regardless of the target. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_L2_MEMCPY_VTCM_CONGESTION 0x819d |
VTCM access from memcopy cannot make progress due to conflicts with VTCM accesses from other sources or credits are all taken. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_PIPE_CONFLICT 0x8095 |
Request not taken by the L2 due to a pipe conflict. The conflict may be a tag bank, data bank, or other pipeline conflict. Supported architectures: V65 V66 V68
| #define ITRACE_DSP_EVENT_PMU_L2_PIPE_CONFLICT_STALL 0x81a6 |
Request is not taken by the L2 cache due to a pipe conflict. The conflict can be a tag bank, data bank, or other pipeline conflict. Supported architectures: V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_BYPASS_RD 0x8182 |
Non-coherent user DMA read access. Access bypassesd the cache hierarchy. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_BYPASS_WR 0x8181 |
Non-coherent user DMA store access. Access bypassed the cache hierarchy. DLBC fetch excluded from this store access. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_RD 0x817f |
Coherent user DMA read access through the cache hierarchy. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_RD_MISS 0x8180 |
Coherent user DMA read access through the cache hierarchy that was a cache miss. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_WR 0x817d |
Coherent user DMA store access through the cache hierarchy. This event includes stores to the descriptor. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_COHERENT_WR_MISS 0x817e |
Coherent user DMA store access through the cache hierarchy that was a cache miss. This event includes stores to the descriptor. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_UDMA_VTCM_CONGESTION 0x819a |
VTCM access from User DMA cannot make progress due to conflicts with VTCM accesses from other sources or credits are all taken. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_DROP 0x80dd |
L2 fetch data dropped because a previous eviction has not completed. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2ITCM_BIMODAL_WRITES_DROPPED 0x80fe |
Number of bimodal writes into L2 ITCM that were dropped. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2ITCM_BIMODAL_WRITES_SUCCESS 0x80fd |
Number of successful bimodal writes into L2 ITCM. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2ITCM_DU_READ 0x80fb |
Number of L2 ITCM read accesses from a DU. Includes all demands and prefetches. This event is not included in any other L2 events. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2ITCM_DU_WRITE 0x80fc |
Number of L2 ITCM write accesses from a DU. Includes stores and dczeroa events. Does not include any cache operations. This event is not included in any other L2 events. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2ITCM_IU_PREFETCH_READ 0x80ff |
Number of ITCM accesses from IU prefetches. Includes only prefetches from an IU. This event is included in event 176. It is not included in any other L2 events. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2ITCM_IU_READ 0x80fa |
Number of ITCM accesses from an IU. Includes IU demand fetches and IU prefetches. This event is not included in any other L2 events. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_LMH_THROTTLE 0x80f2 |
Throttling is based on the value of the peak current that is over the current limits of LMH. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_LOOPCACHE_PACKETS 0x80d6 |
Committed packets were cloned from the packet queue during a pinned hardware loop. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_NUM_PACKET_CRACKED 0x80d9 |
Number of packets that cracked. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_PST_3LDST_L2FIFOCONF_REPLAY 0x81b1 |
Number of times a packet on lower priority cluster had to replay because one cluster had a dual uncacheable loads and the other cluster had a single store or the one cluster had a dual store and other cluster had a load miss. Only increments when store port is present. Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_PST_3STORETYPE_SBCONF_REPLAY 0x81b0 |
Number of times a packet on the lower priority cluster had to replay because one cluster had a dual store and the other cluster had a single store or a memop. Only increments when store port is present. Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_PST_STORE_SENTON_OTHPORT 0x81b2 |
Number of times a slot 0 store was sent to the other store buffer because the other cluster had a slot 1 store or memop. Only increments when store port is present. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_PST_USED_P0P1BUSY 0x81ae |
Number of times a store port was used when p0 and p1 were both occupied. Only increments when store port is present. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SIMPLE_PACKET 0x81d5 |
Number of committed simple packets, which can be dispatched on in-cluster SMT threads. Includes eligible packets that are committed on both primary and in-cluster SMT threads. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_CLUSTER0 0x81c5 |
Number of cycles when more than one packet is committed in cluster 0. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_CLUSTER1 0x81c6 |
Number of cycles when more than one packet is committed in cluster 1. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_CONFLICT_FOR_REG_READ_OR_CU_FWD 0x81c8 |
Number of cases when a packet is SMT-able without slot resource conflicts, but it cannot go due to s0/s1 register read/CU forwarding. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_DU_CONFLICT_PVIEW_CYCLES 0x8099 |
Cycles cluster cannot commit due to a DU resource conflict. Supported architectures: V65 V66 V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_SMT_INTERCLUSTER 0x81c7 |
Number of cycles when packets are committed on both clusters. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_PKT_IQ_NO_PKT_PVIEW_CYCLES 0x81dc |
In-cluster SMT thread is not picked because no packet is in IQ on the SMT thread. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_PKT_NOT_READY_PVIEW_CYCLES 0x81de |
In-cluster SMT thread is not picked because no simple packet is ready for dispatch on the SMT thread. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_PKT_NOT_SIMPLE_PVIEW_CYCLES 0x81dd |
In-cluster SMT thread is not picked because no simple packet is on the SMT thread. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_PKT_PICKED_BUT_NOT_COMMIT_PVIEW_CYCLES 0x81db |
In-cluster SMT thread is picked, but not commmited. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_PKT_REG_FWD_BLOCK_PVIEW_CYCLES 0x81e0 |
In-cluster SMT thread is not picked due to a register and forward block on the SMT thread. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_PKT_SLOT_CONFLICT_PVIEW_CYCLES 0x81df |
In-cluster SMT thread is not picked due to a slot conflict between the primary thread and SMT thread. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_XU_CONFLICT_PVIEW_CYCLES 0x809a |
Cycles cluster could not commit because of XU resource conflict Supported architectures: V65
| #define ITRACE_DSP_EVENT_PMU_STBUF_MATCH_PARTIAL_CRACK_REPLAY 0x8102 |
Number of replays taken by a partial crack store due to a dword match with an existing store buffer entry. Supported architectures: V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_SYSTEM_BUSY_PVIEW_CYCLES 0x80df |
Cycles cluster cannot commit due to system level stalls, including DMA synchronization, ETM is full, Qtimer read is not ready, AXI bus is busy, and global cache operations synchronization. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_TAG_WRITE_CONFLICT_REPLAY 0x80dc |
Number of inter-cluster tag write conflicts. Supported architectures: V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_TAGE_BRANCH_OVERRIDE 0x81ff |
Number of times the TAGE branch predictor overrode the bimodal prediction for a branch instruction. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_TAGE_TABLE_ALLOC 0x81fd |
Number of allocations in the TAGE branch predictor due to mispredicting branches. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_TAGE_TABLE_HIT 0x81fe |
Number of hits in the TAGE branch predictor table. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_THREAD_IDLE_PVIEW_CYCLES 0x81f8 |
Cycles cluster cannot commit because a thread is in the Off , Wait state or in pause. Supported architectures: V75
| #define ITRACE_DSP_EVENT_PMU_THREAD_LMH_THROTTLE 0x80f1 |
For a specific thread, the sustained power exceeds the limits management threshold and limits budget threshold. Results in throttling that is based on thread priority. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_THREAD_OFF_PVIEW_CYCLES 0x8098 |
Cycles cluster cannot commit because a thread is in the Off or Wait state. Supported architectures: V65 V66 V68 V69 V73
| #define ITRACE_DSP_EVENT_PMU_UDMA_ACTIVE_CYCLES 0x8170 |
Cycles user DMA is not idle. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_COHERENT_RD_CYCLES 0x818c |
Cycles user DMA stalled by L2 read. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_COHERENT_WR_CYCLES 0x818d |
Cycles user DMA stalled by L2 write. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DESCRIPTOR_DONE 0x8179 |
User DMA descriptor done. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DLBC_FETCH 0x8185 |
User DMA DLBC fetch. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DLBC_FETCH_CYCLES 0x8186 |
Cycles user DMA stalls due to waiting for a DLBC fetch to return. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMLINK 0x817b |
User DMA DMLink command issued by the core. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMPOLL 0x81b9 |
User DMA DMPoll command issued by the core. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMPOLL_CYCLES 0x8174 |
User DMA DMPoll command cycles. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMRESUME 0x817c |
User DMA DMResume command issued by the core. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMSTART 0x817a |
User DMA DMStart command issued by the core. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMWAIT 0x81ba |
User DMA DMWait command issued by the core. Supported architectures: V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_DMWAIT_CYCLES 0x8175 |
User DMA DMWait command cycles. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_NONCOHERENT_RD_CYCLES 0x818e |
Cycles user DMA stalled by noncoherent read. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_NONCOHERENT_WR_CYCLES 0x818f |
Cycles user DMA stalled by noncoherent write. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_ORDERING_DESCRIPTOR 0x8188 |
The number of descriptors with the ordering bit set. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_PADDING_DESCRIPTOR 0x8189 |
The number of descriptors that use padding/unpadding. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_FULL 0x8195 |
Read buffer fully allocated. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_HALF 0x8193 |
Half of the read buffer allocated. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_HIGH 0x8194 |
3 quarters of the read buffer allocated. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_RD_BUFFER_LEVEL_LOW 0x8192 |
1 quarter of the read buffer allocated. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_STALL_DESCRIPTOR_FETCH 0x8171 |
Cycles user DMA is stalled on descriptor fetch. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_STALL_MONITOR_GUEST_MODE 0x8173 |
Cycles use DMA is stalled in monitor or guest mode Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_STALL_TLB_MISS 0x8172 |
Cycles user DMA is stalled on a TLB miss. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_SYNCHT_CYCLES 0x8176 |
User DMA DMSynchT command cycles. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_TLB_MISS 0x8178 |
User DMA TLB miss count. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_TLBSYNCH_CYCLES 0x8177 |
User DMA DMTLBsynch command cycles. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_UNALIGNED_DESCRIPTOR 0x8187 |
The number of descriptors that generate an unaligned access. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_UNALIGNED_RD 0x818a |
The number of unaligned reads. alignment: 128B for L2/VTCM, 256B for bypass Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_UNALIGNED_WR 0x818b |
The number of unaligned writes. alignment: 128B for L2/VTCM, 256B for bypass Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_RD 0x8184 |
User DMA read access from the VTCM memory. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_RD_CYCLES 0x8190 |
Cycles user DMA stalled by L2 read. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_WR 0x8183 |
User DMA store access to the VTCM memory. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_UDMA_VTCM_WR_CYCLES 0x8191 |
Cycles user DMA stalled by L2 write. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_VMEM_ST_SMT_DU_PORT_CONFLICT_REPLAY 0x81ec |
Number of times any packet takes a replay because CU didn't allocate a port at schedule time and it didn't arbitrate for the port in DU based on the state bit (VMEMSttoVTCM) but needed a port as it mapped to L2. Supported architectures: V73
| #define ITRACE_DSP_EVENT_PMU_VTCM_FIFO_FULL_CYCLES 0x80f9 |
Cycles cluster can be issued if the VTCM FIFO queue is full. Supported architectures: V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_VTCM_SCALAR_FIFO_FULL_CYCLES 0x8092 |
Cycles cluster could issue scalar memory access to vtcm scalar fifo Supported architectures: V65 V66
1.8.13