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itrace
Instrumented Trace
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itrace
Instrumented Trace
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| #define ITRACE_DSP_EVENT_PMU_AHB_8_READ_REQUEST 0x807d |
Number of 8-byte read requests issued by the AHB. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AHB_MULTI_BEAT_READ_REQUEST 0x8086 |
Number of 32-byte multi-beat read requests issued by the AHB. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AHB_READ_REQUEST 0x8024 |
Number of read requests issued by the AHB master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AHB_WRITE_REQUEST 0x8025 |
Number of write requests issued by the AHB master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ANY_DU_REPLAY 0x800d |
Any DU replay. Includes a bank conflict, store buffer full, and so on. Excludes a stall due to a cache miss. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ANY_DU_STALL 0x8063 |
Any DU stall. Increments once when the thread has a DU stall (D-cache miss or DTLB miss). Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ANY_IU_REPLAY 0x800c |
Any IU stall other than an I-cache miss. Includes a jump register stall, fetchcross stall, ITLB miss stall, and so on. Excludes a CU replay. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ARCH_LOCK_PVIEW_CYCLES 0x8088 |
Cycles cluster cannot commit due to a kernel lock or TLB lock. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_CONGESTION 0x802c |
Secondary AXI command or data queue is full. An operation is stuck at the head of the secondary AXI master command queue. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_LINE32_READ_REQUEST 0x8029 |
Number of 32-byte line read requests issued by the secondary AXI master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_LINE32_WRITE_REQUEST 0x802b |
Number of 32-byte line write requests issued by the secondary AXI master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_READ_REQUEST 0x8028 |
All read requests issued by the secondary AXI master. Includes full lines and partial lines. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_READ_BUSY 0x8061 |
AXI secondary slave read access hit a busy line. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_SLAVE_WRITE_BUSY 0x8062 |
AXI secondary slave write access hit a busy line. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI2_WRITE_REQUEST 0x802a |
All write requests issued by the secondary AXI master. Includes full lines and partial lines. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE32_READ_REQUEST 0x8021 |
Number of 32-byte line read requests issued by the primary AXI master. Includes all interleaved requests. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE32_WRITE_REQUEST 0x8023 |
Number of 32-byte line write requests issued by the primary AXI master. Includes all interleaved requests. All bytes are valid. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE64_READ_REQUEST 0x807b |
Number of 64-byte line read requests issued by the primary AXI master. Includes all interleaved requests. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_LINE64_WRITE_REQUEST 0x807c |
Number of 64-byte line write requests issued by the primary AXI master. Includes all interleaved requests. All bytes are valid. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_READ_REQUEST 0x8020 |
All read requests issued by the primary AXI master. Includes full lines, partial lines, and all interleaved requests. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_MULTI_BEAT_ACCESS 0x8026 |
Number of AXI slave multi-beat accesses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_READ_BUSY 0x8058 |
AXI slave read access hit a busy line. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_SINGLE_BEAT_ACCESS 0x8027 |
Number of AXI slave single-beat accesses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_SLAVE_WRITE_BUSY 0x8059 |
AXI slave write access hit a busy line. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_AXI_WRITE_REQUEST 0x8022 |
All write requests issued by the primary AXI master. Includes full lines, partial lines, and all interleaved requests. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_BTB_HIT 0x8037 |
Number of branch target buffer hits. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_BTB_MISS 0x8038 |
Number of branch target buffer misses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE_HIGH_PRIO_EXCEPTION 0x805f |
CLADE high-priority decode that had an exception. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE_HIGH_PRIO_L2_ACCESS 0x805b |
Number of IU or DU requests for a high-priority CLADE region. Not counted for an L2 fetch. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE_HIGH_PRIO_L2_MISS 0x805d |
Number of CLADE high-priority L2 accesses that missed in the L2 cache. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE_LOW_PRIO_EXCEPTION 0x8060 |
CLADE low-priority decode that had an exception. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE_LOW_PRIO_L2_ACCESS 0x805c |
Number of IU or DU requests for a low-priority CLADE region. Not counted for an L2 fetch. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CLADE_LOW_PRIO_L2_MISS 0x805e |
Number of CLADE low-priority L2 accesses that missed in the L2 cacle. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_BIMODAL_BRANCH_INSTS 0x8035 |
Number of committed bimodal branches. Includes *.old and *.new. Increments by two for dual jumps. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_FPS 0x802d |
Number of committed floating point instructions. Increments by two for dual floating-point operations. Excludes conversions. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_INSTS 0x8012 |
Number of committed instructions. Increments by up to eight per cycle. Duplex of two instructions counts as two instructions. Does not include end loops. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_LOADS 0x8016 |
Number of committed load instructions. Includes cached and uncached. Increments by two for dual loads. Excludes prefetches, memory operations, and coprocessor loads. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_MEMOPS 0x8018 |
Number of committed memory operations instructions. Cached or uncached. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_1_THREAD_RUNNING 0x800f |
Number of committed packets with one thread running. Running means the thread is not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_2_THREAD_RUNNING 0x8010 |
Number of committed packets with two threads running. Running means the threads are not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_3_THREAD_RUNNING 0x8011 |
Number of committed packets with three threads running. Running means the threads are not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_4_THREAD_RUNNING 0x8015 |
Number of committed packets with four threads running. Running means the threads are not in Stop or Wait mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_ANY 0x8002 |
Number of packets that are committed by any thread. Packets are executed. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_B2B 0x8006 |
Number of packets that are committed one cycle after the earlier packet in the same thread. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_BSB 0x8003 |
Number of packets that are committed two cycles after an earlier packet in the same thread. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_CHANGED_FLOW 0x801a |
Number of committed packets that resulted in a change of flow. Any taken jump. Includes endloop and dealloc_return. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_ENDLOOP 0x801b |
Number of committed packets containing an end loop that was taken. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_INDIRECT_JUMP 0x8034 |
Number of committed indirect jumps or call instructions. Includes canceled instructions. Does not include JUMPR R31 returns. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_RETURN 0x8033 |
Number of committed return instructions. Includes canceled returns. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PKT_SMT 0x8007 |
Number of packets that are committed on the SMT threads. Includes the second, third, and fourth packets that are committed in one cycle. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PRIVATE_INSTS 0x8014 |
Number of committed instructions that have per-cluster (private) execution resources. Increments by up to eight per cycle. Duplex of two private instructions counts as two private instructions. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_PROGRAM_FLOW_INSTS 0x8019 |
Number of committed packets that contain a program flow instruction. Includes CR jumps, endloop, J, JR, dealloc_return, system/trap, superset of event 56. Dual jumps count as two jumps. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_STORES 0x8017 |
Number of committed store instructions. Includes cached and uncached. Increments by two for dual stores. Excludes memory operations and coprocessor stores. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COMMITTED_TC1_INSTS 0x8013 |
Number of committed TC1 class instructions. Increments by up to eight per cycle. Duplex of two TC1 instructions counts as two separate TC1 instructions. Does not include NOPs. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COPROC0_PKT_XE 0x8090 |
Committed packets on any thread with the XE bit set and XA pointing to Silver context 0. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COUNTER0_OVERFLOW 0x8000 |
Can be used as the event detected by counter1 to build an effective 64-bit counter. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COUNTER2_OVERFLOW 0x8001 |
Can be used as the event detected by counter3 to build an effective 64-bit counter. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COUNTER4_OVERFLOW 0x8004 |
Can be used as the event detected by counter5 to build an effective 64-bit counter. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_COUNTER6_OVERFLOW 0x8005 |
Can be used as the event detected by counter7 to build an effective 64-bit counter. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CU_BUSY_PVIEW_CYCLES 0x808d |
Cycles cluster cannot commit due to a register interlock, register port conflict, bubbles due to a timing class such as tc_3stall, no B2B HVX, or HVX FIFO is full. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CU_PKT_READY_NOT_DISPATCHED 0x800b |
Packets were ready at the CU scheduler but were not scheduled because either the scheduler's thread was not picked or there was an inter-cluster resource conflict. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_1_THREAD_RUNNING 0x801c |
Processor cycles that exactly one thread is running. Running means the thread is not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_2_THREAD_RUNNING 0x801d |
Processor cycles that exactly two threads are running. Running means the threads are not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_3_THREAD_RUNNING 0x801e |
Processor cycles that exactly three threads are running. Running means the threads are not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_CYCLES_4_THREAD_RUNNING 0x801f |
Processor cycles that exactly four threads are running. Running means the threads are not in Wait or Stop mode. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCACHE_DEMAND_MISS 0x8009 |
Number of D-cache cacheable demand primary or secondary misses. Includes dczero stalls. Excludes uncacheables, prefetches, and no-allocate store misses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCACHE_STORE_MISS 0x800a |
Number of D-cache cacheable store misses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCFETCH_COMMITTED 0x8075 |
Number of dcfetches that were committed. Includes hits and drops. Does not include convert-to-prefetches. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCFETCH_HIT 0x8076 |
Number of dcfetch hits in D-cache. Includes hitting valid or reserved lines. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCFETCH_MISS 0x8077 |
Number of dcfetches missed in L1 cache. Counts the dcfetches issued to L2 FIFO. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DCZERO_COMMITTED 0x806c |
Dczeroa instruction was committed. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DTLB_MISS 0x806d |
DTLB miss that goes to JTLB. When both slots miss to different pages, increments by two. When both slots miss to the same page, only counts S1 because S1 goes first and fills for S0. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_BANK_CONFLICT_REPLAY 0x8064 |
DU bank conflict replay. Dual memory access to same bank, but different lines. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_BUSY_OTHER_PVIEW_CYCLES 0x808c |
Cycles cluster cannot commit due to a DU replay, DU bubble, or DTLB miss. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_CACHE_MISS_PVIEW_CYCLES 0x808b |
Cycles cluster cannot commit due to a D-cache cacheable miss. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_CREDIT_REPLAY 0x8065 |
Number of times a packet took a replay because insufficient QoS DU credits were available. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_DEMAND_SECONDARY_MISS 0x8073 |
Number of DU demand secondary misses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_DUAL_LOAD_UNCACHEABLE 0x8079 |
Packets where both loads have addresses uncacheable in the L1 cache Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_FILL_REPLAY 0x8069 |
Fill has an index conflict with an instruction from the same thread in the pipeline. Fills and demands might be from different threads if there is a prefetch from the deferral queue, or if a fill has not be acknowledged for very long and forces itself into the pipeline. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_LOAD_UNCACHEABLE 0x8078 |
Load instructions with addresses uncacheable in the L1 cache. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_MISC_REPLAY 0x8074 |
All DU replays not counted by other replay events. This event counts every time ANY_DU_REPLAY counts and no other DU replay event counts. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_READ_TO_L2 0x806a |
Number of DU reads to L2 cache. Total of everything that brings data from the L2 array. Includes prefetches (dcfetch and hwprefetch). Excludes coprocessor loads. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_SNOOP_REQUEST 0x8068 |
Number of DU snoop requests that were accepted. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_STORE_BUFFER_FULL_REPLAY 0x8067 |
Number of DU replays because a demand load access hit in the store buffer. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_STORE_UNCACHEABLE 0x807a |
Store instructions with addresses uncacheable in the L1 cache. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_UNCACHED_PVIEW_CYCLES 0x808e |
Cycles cluster cannot commit due to a D-cache uncacheable access. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_DU_WRITE_TO_L2 0x806b |
Number of DU writes to L2 cache. Total of everything that is written out of the DU to the L2 array. Includes dczeroa. Excludes dcclean, dccleaninv, tag writes, and coprocessor stores. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_FAST_FETCH_KILLED 0x803a |
Number of fast fetches that were killed (after an I-cache access). Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_FETCH_2_CYCLE 0x803e |
Number of two-cycle fetches in an IU (returns, loop end, fall through, BTB). Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_FETCH_3_CYCLE 0x803f |
Number of three-cycle fetches in an IU. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_FETCHED_PACKETS_DROPPED 0x803b |
Number of packets that are dropped because the IU cannot deliver them to the CU. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_HVX_ACTIVE 0x808f |
VFIFO not empty Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ICACHE_ACCESS 0x8036 |
Number of I-cacheline fetches. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ICACHE_DEMAND_MISS 0x8008 |
Number of I-cache cacheable demand primary or secondary misses. Includes secondary misses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ISSUED_PACKETS 0x800e |
Speculatively issued packets were delivered from an IU. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_ITLB_MISS 0x803d |
Number of ITLB misses that go to JTLB. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_DEMAND_SECONDARY_MISS 0x8039 |
Number of I-cache secondary misses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_NO_PKT_PVIEW_CYCLES 0x808a |
Cycles cluster cannot commit because the issue queue is empty. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_IU_PREFETCHES_SENT_TO_L2 0x803c |
Number of IU prefetches sent to the L2 cache. Includes cachelines not dropped by the L2 cache. Excludes replayed prefetches and only counts prefetches the L2 accepts. Excludes IU prefetches that are sent to L2 ITCM. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_JTLB_MISS 0x8032 |
Instruction or data address translation request was missed in the JTLB. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_ACCESS 0x8049 |
All requests to the L2 cache. Does not include internally generated accesses like L2 fetch, however the programming of the L2Fetch engine is counted. All accesses to odd interleave or even interleave are counted. Can be L2 cacheable or TCM. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_ACCESS_EVEN 0x805a |
Of the events in 0x81, number of accesses made to the even L2 cache. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_CASTOUT 0x804e |
L2 cache evicts a dirty line due to an allocation. This event is not triggered on cache operations. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_LOAD_SECONDARY_MISS 0x8053 |
Number of L2 load secondary misses from a DU. Hit a busy line in the scoreboard, which prevented a return. A busy condition can include pipeline bubbles caused by back-to-back loads, like L1 UC loads. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_LOAD_SECONDARY_MISS_ON_SW_PREFETCH 0x8087 |
Of the events in 0x90, the events where the primary miss was a DC fetch or L2 fetch. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_PREFETCH_ACCESS 0x8051 |
Number of L2 prefetch accesses from a DU. Of the events qualified by 0x7C, the events that are dcfetch and dhwprefetch. These L2 cacheable events target the primary AXI master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_PREFETCH_MISS 0x8052 |
Number of L2 prefetch misses from a DU. Of the events qualified by 0x8D, the events that missed the L2 cache. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_READ_ACCESS 0x8045 |
Number of L2 cacheable read accesses from a DU. Any read access from the DU that might cause a lookup in the L2 cache. Includes loads, L1 prefetches, dcfetches. Excludes the initial L2fetch command, uncacheables, TCM accesses, and coprocessor loads. Must target the primary AXI master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_READ_MISS 0x8046 |
Number of L2 read misses from a DU. Of the events qualified by 0x7C, any event that resulted in an L2 miss (that is, the line was not previously allocated in the L2 cache and will be fetched from the backing memory). Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_STORE_ACCESS 0x804f |
Number of L2 cacheable store access from a DU. Any store access from the DU that might cause a lookup in the L2 cache. Excludes cache operations, uncacheables, TCM, and coprocessor stores. Must target the primary AXI master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_STORE_COALESCE 0x807f |
Number of events from 139 that were coalesced Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_DU_STORE_MISS 0x8050 |
Number of L2 misses from a DU. Of the events qualified by 0x8B, the events that resulted in a miss. Specifically, the cases where the line is not in the cache or a coalesce buffer. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_EVICTION_BUFFERS_FULL 0x8085 |
Counts every cycle when all eviction buffers in any interleave are occupied. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_FIFO_FULL_REPLAY 0x8066 |
Number of L2 even or odd FIFO full replays. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_ACCESS 0x8041 |
Number of L2 cacheable access from an IU. Includes any access to the L2 cache that was the result of an IU command, either demand or L1 prefetch access. Excludes any prefetches generated in the L2 cache. Excludes L2fetch, TCM accesses, and uncacheables. Address must target the primary AXI master. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_MISS 0x8042 |
Number of L2 misses from an IU. Of the events qualified by 0x76, the event that resulted in an L2 miss (demand miss or L1 prefetch miss). An L2 miss is any condition that prevents the immediate return of data to the IU, excluding pipeline conflicts. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_PREFETCH_ACCESS 0x8043 |
Number of prefetches from an IU to the L2 cache. Any IU prefetch access sent to the L2 cache. Access must be L2 cacheable and target the primary AXI. Does not include L2 fetch-generated accesses. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_PREFETCH_MISS 0x8044 |
Number of L2 misses that were IU prefetches. Of the events qualified by 0x78, the events that resulted in an L2 miss. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_IU_SECONDARY_MISS 0x8040 |
Number of L2 secondary misses from an IU. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_70_PERCENT_FULL 0x8081 |
Increments by one for every cycle where the L2 scoreboard is at least 70% full. For a 32-entry scoreboard, 23 or more entries are consumed. This event continues to count even if the scoreboard is more than 80% full. For more than one interleave, this event considers only the scoreboard that has the most entries consumed. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_80_PERCENT_FULL 0x8082 |
Increments by one for every cycle where the L2 scoreboard is at least 80% full. For a 32-entry scoreboard, 26 or more entries are consumed. This event continues to count even if the scoreboard is more than 90% full. For more than one interleave, this event considers only the scoreboard that has the most entries consumed. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_90_PERCENT_FULL 0x8083 |
Increments by one for every cycle where the L2 scoreboard is at least 90% full. For a 32-entry scoreboard, 29 or more entries are consumed. For more than one interleave, this event considers only the scoreboard that has the most entries consumed. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_SCOREBOARD_FULL_REJECT 0x8084 |
L2 scoreboard is too full to accept a selector request, and the selector has a request. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_STORE_LINK 0x8080 |
Number of times a new store links to something else in the scoreboard. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2_TAG_ARRAY_CONFLICT 0x804a |
Of the items in event 130, the items caused by a conflict with the tag array. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_ACCESS 0x8047 |
Number of L2 fetch accesses from a DU. Any access to the L2 cache from the L2 prefetch engine that was initiated by programming the L2Fetch engine. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_ACCESS_CREDIT_FAIL 0x8057 |
L2 fetch access could not get a credit. L2 fetch was blocked due to a missing L2 fetch or L2 evict credit. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND 0x8054 |
Number of L2fetch commands. Excludes L2 fetch stop commands. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND_KILLED 0x8055 |
L2 fetch command was killed because a stop command was issued. Increments once for each L2 fetch command that is killed. If multiple commands are queued to the L2Fetch engine, the kill of each command will be recorded. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND_OVERWRITE 0x8056 |
L2 fetch command was overwritten. Kills an old L2 fetch command and replaces it with a new command. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_COMMAND_PAGE_TERMINATION 0x807e |
L2fetch command terminated because it could not get a page translation from VA to PA. Includes terminations due to permission errors. That is, an address translation can fail because the VA to PA is not in the TLB, or the properties in the translation are not acceptable and the command terminates. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_L2FETCH_MISS 0x8048 |
Number of L2 fetch misses from a programmed inquiry. Of the events qualified by 0x7E, the event that resulted in an L2 miss (that is, the line was not previously allocated in the L2 cache and will be fetched from the backing memory). Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_PAGE_CROSS_REPLAY 0x8072 |
Page cross from a valid packet that caused a replay. Excludes pdkill packets. Counts twice if both slots cause a page cross. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_PORT_CONFLICT_REPLAY 0x8071 |
Number of all port conflict replays, including the same cluster replays caused by high-priority fills and store buffer force drains. Includes inter-cluster replays. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_REDIRECT_BIMODAL_MISPREDICT 0x802e |
Mispredicted bimodal branch direction caused a control flow redirect. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_REDIRECT_LOOP_MISPREDICT 0x8030 |
Mispredicted hardware loop end caused a control flow redirect. Can only happen when the loop has few packets and the loop count is 2 or less. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_REDIRECT_MISC 0x8031 |
Control flow is redirected for a reason other than events 81, 82, and 83. Includes exceptions, traps, interrupts, non-R31 jumps, multiple initialization loops in flight, and so on. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_REDIRECT_PVIEW_CYCLES 0x8089 |
Cycles cluster cannot commit because of redirects such as branch mispredicts. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_REDIRECT_TARGET_MISPREDICT 0x802f |
Mispredicted branch target caused a control flow redirect. Includes an RAS mispredict, and HintJR mispredict. Excludes indirect jumps and calls other than JUMPR R31 returns. Excludes direction mispredicts. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_SMT_BANK_CONFLICT 0x8070 |
Number of inter-thread SMT bank conflicts. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_STORE_BUFFER_FORCE_REPLAY 0x806f |
Store buffer must drain, forcing the current packet to replay. Typically occurs on a cache index match between the current packet and store buffer. Can also a store buffer timeout. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_STORE_BUFFER_HIT_REPLAY 0x806e |
Store buffer hit is replayed because a packet with two stores is going to the same bank but different cachelines, followed by a load from an address that was pushed into the store buffer. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_TCM_DU_ACCESS 0x804b |
Number of TCM accesses from a DU. DU access to the L2 TCM space. Excludes HVX requests. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_TCM_DU_READ_ACCESS 0x804c |
Number of TCM read accesses from a DU. DU read access to the L2 TCM space. Includes HVX requests. Supported architectures: V65 V66 V68 V69 V73 V75
| #define ITRACE_DSP_EVENT_PMU_TCM_IU_ACCESS 0x804d |
Number of TCM accesses from an IU. IU access to the L2 TCM space. Supported architectures: V65 V66 V68 V69 V73 V75
1.8.13