itrace_cpu_events_la.h File Reference

CPU event definitions for LA/LE. More...

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Macros
#define	ITRACE_CPU_EVENT_SYSFS_CORE_0_CLK_FREQ_HZ   0x0
	Clock frequency (in Hz) of core 0.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_1_CLK_FREQ_HZ   0x1
	Clock frequency (in Hz) of core 1.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_2_CLK_FREQ_HZ   0x2
	Clock frequency (in Hz) of core 2.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_3_CLK_FREQ_HZ   0x3
	Clock frequency (in Hz) of core 3.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_4_CLK_FREQ_HZ   0x4
	Clock frequency (in Hz) of core 4.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_5_CLK_FREQ_HZ   0x5
	Clock frequency (in Hz) of core 5.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_6_CLK_FREQ_HZ   0x6
	Clock frequency (in Hz) of core 6.
#define	ITRACE_CPU_EVENT_SYSFS_CORE_7_CLK_FREQ_HZ   0x7
	Clock frequency (in Hz) of core 7.
#define	ITRACE_CPU_EVENT_SYSFS_CLK_FREQ_HZ   0x8
	Clock frequency (in Hz) of current core.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_0_CLK_FREQ_HZ   0x9
	Clock frequency (in Hz) of core 0.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_1_CLK_FREQ_HZ   0xa
	Clock frequency (in Hz) of core 1.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_2_CLK_FREQ_HZ   0xb
	Clock frequency (in Hz) of core 2.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_3_CLK_FREQ_HZ   0xc
	Clock frequency (in Hz) of core 3.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_4_CLK_FREQ_HZ   0xd
	Clock frequency (in Hz) of core 4.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_5_CLK_FREQ_HZ   0xe
	Clock frequency (in Hz) of core 5.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_6_CLK_FREQ_HZ   0xf
	Clock frequency (in Hz) of core 6.
#define	ITRACE_CPU_EVENT_FTRACE_CORE_7_CLK_FREQ_HZ   0x10
	Clock frequency (in Hz) of core 7.
#define	ITRACE_CPU_EVENT_FTRACE_CLK_FREQ_HZ   0x11
	Clock frequency (in Hz) of current core.
#define	ITRACE_CPU_EVENT_PERF_SW_TASK_CLOCK   0x12
	Clock count specific to the current task.
#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS   0x13
	Page fault count.
#define	ITRACE_CPU_EVENT_PERF_SW_CONTEXT_SWITCHES   0x14
	Context switches count.
#define	ITRACE_CPU_EVENT_PERF_SW_CPU_MIGRATIONS   0x15
	Count for the number of times the process has migrated to a new CPU.
#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MIN   0x16
	Minor page fault count.
#define	ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MAJ   0x17
	Major page fault count.
#define	ITRACE_CPU_EVENT_PERF_SW_ALIGNMENT_FAULTS   0x18
	Alignment fault count.
#define	ITRACE_CPU_EVENT_PERF_SW_EMULATION_FAULTS   0x19
	Emulation fault count.
#define	ITRACE_CPU_EVENT_PERF_HW_CPU_CYCLES   0x1a
	Cycle count.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_REFERENCES   0x1b
	Cache references.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_MISSES   0x1c
	Cache misses.
#define	ITRACE_CPU_EVENT_PERF_HW_BRANCH_MISSES   0x1d
	Branch misses.
#define	ITRACE_CPU_EVENT_PERF_HW_BUS_CYCLES   0x1e
	Bus cycle count.
#define	ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_FRONTEND   0x1f
	Stalled cycles during issue.
#define	ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_BACKEND   0x20
	Stalled cycles during retirement.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_ACCESS   0x21
	Level 1 Data Cache Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_MISS   0x22
	Level 1 Data Cache Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_ACCESS   0x23
	Level 1 Instruction Cache Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_MISS   0x24
	Level 1 Instruction Cache Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_ACCESS   0x25
	Last-Level Cache Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_MISS   0x26
	Last-Level Cache Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_ACCESS   0x27
	Data TLB Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_MISS   0x28
	Data TLB Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_ACCESS   0x29
	Instruction TLB Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_MISS   0x2a
	Instruction TLB Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_ACCESS   0x2b
	Branch Prediction Unit Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_MISS   0x2c
	Branch Prediction Unit Read Misses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_ACCESS   0x2d
	Local Memory Read Accesses.
#define	ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_MISS   0x2e
	Local Memory Read Misses.
#define	ITRACE_NUMBER_DEFINED_CPU_EVENTS   0x2f
	Number of supported CPU events.
#define	MAX_NUMBER_CPU_PMUS   3
	Maximum number of hardware events that can monitored.

Detailed Description

CPU event definitions for LA/LE.

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itrace_cpu_events_la.h

Note: This file is automatically generated.

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