itrace_cpu_events_la.h

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#ifndef ITRACE_CPU_EVENTS_LA_H
#define ITRACE_CPU_EVENTS_LA_H


#define ITRACE_CPU_EVENT_SYSFS_CORE_0_CLK_FREQ_HZ   0x0
#define ITRACE_CPU_EVENT_SYSFS_CORE_1_CLK_FREQ_HZ   0x1
#define ITRACE_CPU_EVENT_SYSFS_CORE_2_CLK_FREQ_HZ   0x2
#define ITRACE_CPU_EVENT_SYSFS_CORE_3_CLK_FREQ_HZ   0x3
#define ITRACE_CPU_EVENT_SYSFS_CORE_4_CLK_FREQ_HZ   0x4
#define ITRACE_CPU_EVENT_SYSFS_CORE_5_CLK_FREQ_HZ   0x5
#define ITRACE_CPU_EVENT_SYSFS_CORE_6_CLK_FREQ_HZ   0x6
#define ITRACE_CPU_EVENT_SYSFS_CORE_7_CLK_FREQ_HZ   0x7
#define ITRACE_CPU_EVENT_SYSFS_CLK_FREQ_HZ   0x8

#define ITRACE_CPU_EVENT_FTRACE_CORE_0_CLK_FREQ_HZ   0x9
#define ITRACE_CPU_EVENT_FTRACE_CORE_1_CLK_FREQ_HZ   0xa
#define ITRACE_CPU_EVENT_FTRACE_CORE_2_CLK_FREQ_HZ   0xb
#define ITRACE_CPU_EVENT_FTRACE_CORE_3_CLK_FREQ_HZ   0xc
#define ITRACE_CPU_EVENT_FTRACE_CORE_4_CLK_FREQ_HZ   0xd
#define ITRACE_CPU_EVENT_FTRACE_CORE_5_CLK_FREQ_HZ   0xe
#define ITRACE_CPU_EVENT_FTRACE_CORE_6_CLK_FREQ_HZ   0xf
#define ITRACE_CPU_EVENT_FTRACE_CORE_7_CLK_FREQ_HZ   0x10
#define ITRACE_CPU_EVENT_FTRACE_CLK_FREQ_HZ   0x11

#define ITRACE_CPU_EVENT_PERF_SW_TASK_CLOCK   0x12
#define ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS   0x13
#define ITRACE_CPU_EVENT_PERF_SW_CONTEXT_SWITCHES   0x14
#define ITRACE_CPU_EVENT_PERF_SW_CPU_MIGRATIONS   0x15
#define ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MIN   0x16
#define ITRACE_CPU_EVENT_PERF_SW_PAGE_FAULTS_MAJ   0x17
#define ITRACE_CPU_EVENT_PERF_SW_ALIGNMENT_FAULTS   0x18
#define ITRACE_CPU_EVENT_PERF_SW_EMULATION_FAULTS   0x19

#define ITRACE_CPU_EVENT_PERF_HW_CPU_CYCLES   0x1a
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_REFERENCES   0x1b
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_MISSES   0x1c
#define ITRACE_CPU_EVENT_PERF_HW_BRANCH_MISSES   0x1d
#define ITRACE_CPU_EVENT_PERF_HW_BUS_CYCLES   0x1e
#define ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_FRONTEND   0x1f
#define ITRACE_CPU_EVENT_PERF_HW_STALLED_CYCLES_BACKEND   0x20

#define ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_ACCESS   0x21
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_L1D_READ_MISS   0x22
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_ACCESS   0x23
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_L1I_READ_MISS   0x24
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_ACCESS   0x25
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_LL_READ_MISS   0x26
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_ACCESS   0x27
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_DTLB_READ_MISS   0x28
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_ACCESS   0x29
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_ITLB_READ_MISS   0x2a
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_ACCESS   0x2b
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_BPU_READ_MISS   0x2c
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_ACCESS   0x2d
#define ITRACE_CPU_EVENT_PERF_HW_CACHE_NODE_READ_MISS   0x2e

#define ITRACE_NUMBER_DEFINED_CPU_EVENTS   0x2f


#define MAX_NUMBER_CPU_PMUS                     3

#endif